Spacer-Based Patterning for Tight-Pitch RAM Bit Cells
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Solution Overview
Problem
Current integrated circuit fabrication techniques face challenges in achieving tight-pitch and low-variability random access memory (RAM) bit cells, particularly in reducing size and pitch while maintaining reliability, due to limitations in lithography resolution and issues with non-volatility, soft error rates, and endurance in memory devices.
Innovation Solution
The implementation of spacer-based patterning methods, which involve forming spacers along the sidewalls of features to define the edges of memory bit cells, allowing for tighter pitch division and reduced variability, enabling the creation of high-density arrays of non-volatile RAM bit cells through multiple patterning steps and hardmask layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography patterning is used, then manufacturing process is simpler, but pitch and variability cannot be reduced sufficiently for tight-pitch RAM bit cells
Solution Approach 1:
The patterning process is segmented into multiple distinct steps: forming mandrels at a first pitch, depositing spacers on mandrel sidewalls, selectively removing alternating mandrels, and repeating the process. This segmentation allows each step to optimize for specific precision requirements, achieving tight-pitch control while managing overall process complexity through systematic breakdown of the fabrication sequence.
Solution Approach 2:
The invention transitions from planar 2D patterning to 3D spacer-based patterning by depositing vertical spacers on mandrel sidewalls. This dimensional transition enables pitch division by a factor of two or more, as the spacer width is determined by conformal deposition thickness rather than lithographic resolution, thereby achieving tighter pitch control through vertical dimension exploitation.
2Quantity of substance
If feature size is reduced to increase density, then capacity increases, but variability and reliability deteriorate
Solution Approach 1:
The spacer structures self-align to the mandrel features through conformal deposition, automatically defining their position and width based on mandrel geometry and deposition thickness. This self-service mechanism eliminates alignment errors between patterning steps and ensures uniform spacer dimensions across the wafer, thereby reducing variability while increasing density through tighter pitch.
3Quantity of substance
If pitch is reduced to increase density, then capacity increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The invention changes the controlling parameter for pitch from lithographic critical dimension (CD) to spacer deposition thickness. By using atomic layer deposition or chemical vapor deposition to form spacers, the pitch is controlled by precisely controllable film thickness parameters rather than optical resolution limits, enabling tighter pitch control with better manufacturing precision through material deposition process control.
Data Source
AI summary
Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.