SPAD Pixel Isolation Structure for High Fill-Factor CMOS Integration
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Solution Overview
Problem
Designing high-resolution sensor arrays with SPAD pixels is challenging due to the large size and high voltage operation of SPADs, which requires significant spacing and results in low fill-factor and high power consumption, especially when integrating PMOS with SPADs, and existing stacked configurations are expensive.
Innovation Solution
A CMOS image sensor pixel cell with a semiconductor substrate featuring a shallow trench isolation structure and implant regions that isolate CMOS transistor regions from SPADs, allowing for compact integration of both NMOS and PMOS transistors with SPADs, and using a shared cathode ring for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sufficient spacing is provided between SPAD and surrounding transistors to prevent breakdown and leakage, then reliability is improved, but pixel area increases resulting in lower fill-factor
Solution Approach 1:
An isolation structure comprising a first shallow trench isolation structure, a p-type semiconductor region, a second shallow trench isolation structure, and an implant region is introduced as an intermediary between the SPAD and surrounding transistors. This isolation structure provides sufficient electrical isolation to prevent breakdown and leakage while occupying minimal space, thereby maintaining high reliability without significantly increasing pixel area
Solution Approach 2:
The isolation structure is nested within the pixel region in a compact arrangement where the p-type semiconductor region is positioned between the first and second shallow trench isolation structures, which are themselves positioned adjacent to the SPAD and transistor regions. This nested configuration maximizes space utilization while providing the required isolation
2Ease of manufacture
If NMOS-only circuits are used for easier isolation from SPAD, then ease of manufacture is improved, but power consumption increases
Solution Approach 1:
The isolation structure with p-type semiconductor regions and shallow trench isolation structures serves as an effective intermediary that provides sufficient electrical isolation between the SPAD and both NMOS and PMOS transistors. This enables the use of complete CMOS circuits (both NMOS and PMOS) rather than being restricted to NMOS-only circuits, thereby reducing power consumption while maintaining ease of isolation
Solution Approach 2:
The invention changes the isolation parameters by using a combination of shallow trench isolation structures and doped semiconductor regions with specific doping types and concentrations. This optimized isolation configuration provides sufficient electrical isolation for CMOS circuits operating at high voltage, enabling lower power consumption through the use of both NMOS and PMOS transistors
3Reliability
If wide separation is provided between SPAD cathode and N-well to prevent punch-through leakage, then reliability is improved, but pixel pitch increases resulting in lower fill-factor
Solution Approach 1:
The p-type semiconductor region acts as an intermediary barrier between the SPAD cathode and the N-well, preventing direct interaction that would cause punch-through leakage. This localized isolation mechanism provides sufficient reliability to prevent leakage while occupying minimal space, avoiding the need for wide separation that would increase pixel pitch
Solution Approach 2:
The isolation is applied locally at the critical interface between the SPAD cathode and N-well using a p-type semiconductor region positioned precisely where needed. This localized approach provides effective leakage prevention without requiring global increases in pixel pitch, maintaining compact dimensions
Data Source
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AI summary
A pixel cell for a CMOS image sensor comprises: a semiconductor substrate having a first side and a second side opposite the first side; a first pixel region including at least one first photodiode, the first photodiode comprising a first region formed from a first type semiconductor on the first side of the semiconductor substrate and a second region formed from a second type semiconductor on the first side of the semiconductor substrate; a pixel transistor region including at least one transistor; and an isolation structure that isolates the pixel transistor region from the first photodiode, the isolation structure on the first side of the semiconductor substrate comprising a first shallow trench isolation, STI, structure that is proximate to the second region of the first photodiode, a third region formed from the first type semiconductor that is proximate to the first STI structure, a second STI structure that is proximate to the third region and that is proximate to the pixel transistor region, and an implant region formed from the first type semiconductor that is in contact with the third region and extends toward the second side of the semiconductor substrate.