SPAD Quench Circuit With Variable RC Hold-Off and Fast Recharge
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Solution Overview
Problem
Fully depleted single photon avalanche diodes (SPADs) suffer from low quench efficiency, resulting in dual voltage peaks and prolonged dead time, which limits photodetection rate, as existing passive and active quenching circuits either fail to achieve full quench or increase dead time.
Innovation Solution
An active quenching circuit with a variable RC time constant, incorporating a starved delayed buffer and transistors, allows for a low RC time constant during quenching, a high time constant during hold-off, a low RC time constant during recharge, and a capacitor for passive recharge, enabling full quenching with a short dead time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large quenching resistor is used to assist quenching, then quenching efficiency is improved, but recharge time increases
Solution Approach 1:
The patent applies dynamics by making the quenching resistance variable rather than fixed. The resistance automatically adjusts between a first resistance value during quenching (to ensure full charge carrier removal) and a second resistance value during recharge (to minimize recharge time). This dynamic adjustment resolves the contradiction by optimizing both quenching efficiency and recharge speed at different operational phases.
Solution Approach 2:
The patent changes the resistance parameter over time based on the operational state of the SPAD. By transitioning the quenching resistance between two distinct values depending on whether the SPAD is in quenching or recharge mode, the system achieves both thorough quenching and rapid recharge, effectively resolving the time-efficiency tradeoff.
2Reliability
If passive quenching circuits are used to ensure full quench, then quenching completeness is improved, but dead time increases
Solution Approach 1:
The patent transforms the static passive quenching approach into a dynamic system where the resistance value changes based on operational phase. During quenching, the first resistance value ensures complete charge carrier removal. During recharge, the second resistance value minimizes dead time. This dynamic behavior maintains quenching completeness while significantly improving photodetection rate.
3Productivity
If active quenching systems are used to reduce dead time, then photodetection rate is improved, but quenching completeness may be compromised
Solution Approach 1:
The patent employs dynamic resistance switching to achieve both rapid response and complete quenching. The circuit transitions between resistance states based on the SPAD's operational phase, ensuring that during quenching the resistance provides thorough charge carrier removal, while during recharge it enables fast response. This resolves the contradiction between photodetection rate and quenching completeness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The active quenching circuit effectively fully quenches the SPAD, maintaining a short dead time and enhancing photodetection rate by alternating RC time constants and utilizing a starved delayed buffer for efficient charge removal.
Implementation Method 1
a capacitor coupled between the node and ground
Implementation Method 2
When a photon-generated carrier (via the internal photoelectric effect) is injected into the depletion region of the PN junction
Implementation Method 3
a self-sustaining avalanche is caused, and detection of this avalanche can be used to indicate detection of the photon that generated the carrier
Data Source
AI summary
A photodetection circuit includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage supply through a quench resistance and an anode coupled to a first node, a capacitive deep trench isolation capacitor coupled between the first node and ground, and a first n-channel transistor. The first n-channel transistor has a drain coupled to the first node, a source coupled to ground, and a gate coupled to a resistance control signal. A second n-channel transistor has a drain coupled to the first node, a source coupled to ground, and a gate coupled to a second node. An inverter has an input coupled to the first node and an output coupled to an intermediate node. A current starved inverter has an input coupled to the intermediate node and an output coupled to the second node.