Reconfigurable Spare Gate Cell Layout for Low-Area ECO Logic
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Solution Overview
Problem
Current integrated circuit designs require multiple spare cells to perform different logic functions, leading to high silicon area and power consumption, as well as the need for costly photo mask changes during Engineering Change Orders (ECOs), due to the limitation of each spare cell performing only one functionality at a time.
Innovation Solution
A spare cell with at least two inputs and two outputs is designed to concurrently perform multiple logic functions by selecting different connections of its inputs, allowing for various functionalities to be implemented without modifying internal nodes, thus reducing the need for costly photo mask changes and minimizing silicon area and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple spare cells are used to perform different logic functions, then logic function versatility is improved, but silicon area and power consumption increase
Solution Approach 1:
The patent implements a universal spare gate cell that can perform multiple logic functions (NAND, NOR, inverter, XOR, XNOR, buffer) through configurable connections. The cell uses a standardized transistor structure with selectable interconnections achieved through metal layer routing, allowing one cell to replace multiple dedicated spare cells, thereby reducing silicon area while maintaining versatility for ECO operations
2Adaptability or versatility
If multiple spare cells are used to perform different logic functions, then logic function versatility is improved, but power consumption increases
Solution Approach 1:
The universal spare gate cell design reduces power consumption by eliminating the need for multiple dedicated spare cells. Each universal cell consumes power only when actively configured and used for a specific logic function, whereas multiple dedicated cells would consume standby power even when not in use. The configurable connection structure allows dynamic activation of only the required functionality
3Reliability
If photo masks are changed to implement ECOs, then design correctness is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the circuit design into base layers (cell structures) and interconnect layers (metal routing). The spare gate cells are pre-defined in the base layers with standardized structures, while the specific logic function is determined by metal layer connections. This segmentation allows ECOs to be implemented by changing only metal layer routes rather than requiring costly photo mask changes to the base cell structures
Solution Approach 2:
The patent implements dynamic reconfigurability through metal layer routing that can be modified after silicon fabrication. The spare gate cells maintain fixed transistor structures in the base layers, but their functional behavior is dynamically changed by altering metal interconnect patterns, enabling post-manufacturing design corrections without re-fabrication
Data Source
AI summary
Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously.