Asynchronous SPDIF Clock Recovery Without PLL
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Solution Overview
Problem
Conventional data recovery systems rely on Phase-Locked Loops (PLL) that are prone to jitter and other failure mechanisms, requiring costly and complex clock synchronization, which is inefficient for handling bursty or irregular data streams.
Innovation Solution
A data recovery system that acquires data without synchronization to the input data stream frequency, using a digital oversampler, sample receiver, and sample rate converter with a 'toothless' clock signal generated by a rate generator, eliminating the need for PLL and reducing power and expense while handling various data stream characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Phase-Locked Loop (PLL) is used for clock synchronization in data recovery, then data synchronization is achieved, but jitter and phase noise increase, reducing reliability
Solution Approach 1:
The patent extracts and removes the PLL component from the data recovery system. Instead of using a PLL to synchronize the sampling clock to the incoming data stream, the system samples data asynchronously without requiring clock synchronization, thereby eliminating the source of jitter and phase noise while maintaining data recovery reliability
Solution Approach 2:
The patent replaces the mechanical/analog PLL synchronization mechanism with a digital asynchronous sampling approach. The system uses a simple counter to track the number of valid data samples received and reconstructs the data stream without requiring the sampling clock to be locked to the input data frequency, substituting complex analog synchronization with simpler digital processing
2Reliability
If a PLL-based clock synchronization system is implemented, then data recovery is enabled, but device complexity and cost increase
Solution Approach 1:
The patent removes the entire PLL-based clock synchronization subsystem from the data recovery architecture. The system achieves data recovery without requiring the sampling clock frequency to match the input data stream frequency, eliminating complex phase detectors, charge pump circuits, and voltage-controlled oscillators
Solution Approach 2:
The system uses a simple counter that automatically tracks the number of valid data samples received during each sampling period. This self-service mechanism requires no external clock synchronization or complex control logic, as the counter naturally adapts to varying input data rates and bursty traffic patterns
3Reliability
If PLL-based synchronization is used, then clock frequency matching is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the power-hungry PLL circuitry from the system. The asynchronous sampling approach requires only a simple counter and basic digital logic, consuming significantly less power than the continuous operation of phase detectors, charge pumps, and VCOs in a PLL system
Solution Approach 2:
The system uses a simple, low-cost counter mechanism instead of expensive and power-intensive PLL components. The counter is a basic digital element that consumes minimal power compared to the analog circuitry required for clock synchronization, making the overall system more energy-efficient
Data Source
AI summary
A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.