Splice Interposer Pillars for Semiconductor Die Interconnect
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Solution Overview
Problem
The production of large interposers for semiconductor packages is challenging due to their excessive size, high sensitivity to defects, and the need for expensive masks, which complicates the creation of fine pitch interconnects between devices, especially when not all connections are necessary, such as pass-through connections in central regions.
Innovation Solution
A method involving a splice interposer with varying height pillars is used to connect semiconductor dies to a substrate and each other, allowing for efficient interconnection and wiring while minimizing the size of the interposer, using pillars of different heights to attach the dies to both the substrate and the interposer, and allowing for separate processing and testing of each modular component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If large interposers are used to provide fine pitch redistribution, then interconnect density is improved, but manufacturing complexity and cost increase due to excessive size and defect sensitivity
Solution Approach 1:
The patent divides the interposer structure into modular components: multiple semiconductor dies are separately processed and tested, then interconnected through a laminate structure. This segmentation allows each die to be manufactured and validated independently, reducing the complexity of manufacturing large monolithic interposers while achieving high interconnect density through fine pitch connections between multiple smaller dies.
2Area of stationary object
If integral interposer units are used, then full area coverage is achieved, but productivity decreases due to few interposers per wafer and high defect sensitivity
Solution Approach 1:
Instead of manufacturing few large integral interposers per wafer, the patent segments the interconnection function across multiple smaller semiconductor dies. Each die can be processed independently on standard wafers, significantly increasing the number of units produced per wafer. The modular approach reduces defect sensitivity since a defect in one die does not compromise the entire interposer assembly.
Solution Approach 2:
The patent employs a nested structure where multiple semiconductor dies are interconnected within a laminate package. The dies are arranged and connected in a hierarchical manner, with each die containing its own interconnect structure, and the collective assembly providing the full area coverage function previously requiring a single large interposer.
3Adaptability or versatility
If embedded bridge chip interposers are used, then subsurface interconnection is achieved, but device complexity increases due to complicated processing for single sided interconnect
Solution Approach 1:
The patent separates the interconnection functions into distinct modular components rather than embedding a complex bridge chip structure. Each semiconductor die is independently processed with standard interconnect techniques, and the laminate provides the interconnection medium. This segmentation eliminates the need for complicated embedded processing while achieving versatile interconnection capabilities between multiple dies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of interposers while maintaining high interconnect density, simplifies manufacturing by allowing staged testing, and avoids full build defects, enabling efficient chip-to-chip connections and mechanical integrity between dies and laminate.
Implementation Method 1
The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor die
Implementation Method 2
The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate
Data Source
AI summary
A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.