3D-NAND Split Channel Gates for Alignment Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As 3D-NAND flash memory devices exceed 100 layers, managing trade-offs among etch profile control, size uniformity, and productivity becomes increasingly challenging, particularly due to alignment issues of channel holes in different stacks and connection issues based on double patterns, which affect bit density and cost.
Innovation Solution
The implementation of a 3D-NAND memory device with split channel gates and a method of manufacturing that includes forming channel structures with concentrically arranged storage structures separated by isolation structures, allowing for increased bit density by splitting channel structures into multiple sections, thereby improving alignment and connection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cell layers of 3D-NAND exceed 100 layers to increase bit density, then the storage capacity is improved, but the alignment issue of channel holes in different stacks and connection issue based on double pattern worsen
Solution Approach 1:
The patent divides each channel structure into multiple independent channel sections separated by isolation structures. This segmentation allows each channel section to be formed and aligned independently, reducing the cumulative alignment error that occurs in traditional continuous channel structures exceeding 100 layers. The isolation structures act as reference points for subsequent stacking processes, improving overall alignment precision.
Solution Approach 2:
The patent introduces isolation structures as intermediary elements between channel sections. These isolation structures serve as mediators that facilitate precise alignment and connection between different stacks by providing a standardized interface and reference geometry for the double pattern process, thereby resolving the alignment and connection issues.
2Ease of manufacture
If traditional continuous channel structures are used, then the manufacturing process is simpler, but the bit density and alignment precision deteriorate
Solution Approach 1:
By segmenting the channel structure into multiple channel sections separated by isolation structures, the patent enables independent formation and alignment of each section. This segmentation approach maintains manufacturing simplicity through standardized repeating units while significantly increasing bit density by allowing more precise packing and stacking of channel structures.
3Quantity of substance
If the number of channel holes is increased based on double pattern, then the bit density is improved, but the connection issue and alignment precision worsen
Solution Approach 1:
The isolation structures introduced in the patent serve as intermediary elements that ensure reliable connections between channel sections. By providing a standardized interface and reference geometry, these intermediaries enable precise alignment and robust electrical connections, thereby improving connection reliability even as the number of channel holes increases through double patterning.
Solution Approach 2:
The isolation structures are designed to automatically provide alignment references and connection interfaces for subsequent stacking processes. This self-service capability ensures that each channel section can be independently aligned and connected without requiring complex external alignment procedures, thereby maintaining high connection reliability as bit density increases.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. A first channel structure of the semiconductor device extends along a first vertical axis in the vertical direction through the word line layers and the insulating layers. The first channel structure includes a plurality of storage structures and a first isolation structure. The storage structures are arranged around the first isolation structure. The first isolation structure extends along the first vertical axis and separates the storage structures from one another.