Split-Gate Flash Memory Array Bit Line Sharing
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Solution Overview
Problem
The challenge in memory design is to reduce the area of memory arrays while maintaining efficient reading, programming, and erasing operations, as the area of the memory array directly affects the cost of memory devices.
Innovation Solution
A memory array design that incorporates a plurality of flash memory cells, each comprising a first and second split-gate flash memory cell, sharing bit lines to minimize the number of bit lines and optimize voltage configurations for reading, programming, and erasing, thereby reducing the overall area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each split-gate flash memory cell is connected with two separate bit lines, then the reading and programming operations can be performed independently, but the area of the memory array increases
Solution Approach 1:
The patent merges the bit line connections by having adjacent flash memory cells share common bit lines. Specifically, the drain of one cell and the source of the adjacent cell connect to the same bit line, reducing the total number of bit lines required while maintaining the ability to perform independent reading and programming operations through selective voltage application.
Solution Approach 2:
The shared bit lines serve multiple functions: they act as drain connections for one cell and source connections for adjacent cells, enabling both reading and programming operations on different cells simultaneously through appropriate voltage configuration, thus making the bit lines multi-functional.
2Area of stationary object
If the number of bit lines is reduced by sharing, then the memory array area decreases, but the voltage configuration complexity increases
Solution Approach 1:
The patent segments the voltage application strategy into distinct phases: during reading operations, specific bit lines are selected and configured with read voltages while others remain at ground; during programming, different voltage configurations are applied. This segmentation of operational phases simplifies the control logic despite the shared infrastructure.
Solution Approach 2:
The patent employs dynamic voltage configuration where the function of each bit line changes based on the operation mode (read vs. program) and the selected cell. The same physical bit line can serve as a drain for one cell during programming while serving as a source for an adjacent cell during reading, with voltages dynamically adjusted to achieve the desired functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively reduces the area of the memory array, decreases costs, and improves memory yield by sharing bit lines and using efficient voltage configurations, ensuring accurate read and programming operations without additional voltage sources.
Implementation Method 1
the programming via source-side hot electron injection
Implementation Method 2
selecting a first memory bit of the first split-gate flash memory cell by configuring voltages on the first bit line, the second bit line, the word line, the first control gate line, and the second control gate line, so that the first memory bit of the first split-gate flash memory cell is in a to-be-read state
Implementation Method 3
configuring a voltage on the third bit line to prevent memory bits of the second split-gate flash memory cell from being in a to-be-read state
Data Source
AI summary
A memory array and a method for reading, programming and erasing the same are provided. The memory array includes flash memory cells arranged in an array, each flash memory cell includes a first and a second split-gate flash memory cell; a first control gate of the first split-gate flash memory cell is connected with a first control gate of the second split-gate flash memory cell and a first control gate line, a second control gate of the first split-gate flash memory cell is connected with a second control gate of the second split-gate flash memory cell and a second control gate line; a word line gate of the first split-gate flash memory cell is connected with a word line gate of the second split-gate flash memory cell and a word line; two drains of the first and second split-gate flash memory cells share a same bit line.