Split Gate Flash Memory Cell Erase Gate Overhang Design

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Solution Overview

Problem

Existing split gate non-volatile flash memory cells do not effectively enhance erase efficiency due to the lack of a specific dimensional relationship between the erase gate and the floating gate.

Innovation Solution

A split gate non-volatile memory cell design with an erase gate having a portion that overhangs the floating gate, where the ratio of the overhang length to the vertical distance between the overhang and the floating gate is between approximately 1.0 and 2.5, enhancing the erase efficiency by improving the local electrical field and electron tunneling mechanism.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the erase gate is positioned close to the floating gate to enhance erase efficiency, then the erase performance improves, but the risk of unintended charge injection or interference with the floating gate increases

Engineering Contradiction:

Improveerase efficiencyVSAvoidcharge injection interference

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The erase gate is designed with a non-uniform structure featuring an overhang portion that extends laterally over the floating gate. This creates localized regions of different electrical characteristics: the overhang portion generates a concentrated electric field directly over the floating gate for efficient erasure, while the spaced portions maintain safe distances to prevent harmful charge injection. The insulating layer beneath the erase gate provides localized electrical isolation where needed.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The erase gate structure transitions from a conventional planar configuration to a three-dimensional configuration with lateral overhang. This dimensional change allows the erase gate to achieve dual functionality: the overhang portion provides close proximity for enhanced erase efficiency, while the spaced portions maintain adequate separation to prevent interference. The vertical stacking with insulating layers adds another dimension of control over electrical field distribution.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If a conventional erase gate configuration is used, then the device structure remains simple, but the erase efficiency is insufficient due to inadequate electric field concentration

Engineering Contradiction:

Improveerase efficiencyVSAvoiderase gate structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The erase gate incorporates an overhang portion that extends laterally over the floating gate, creating a localized region of concentrated electric field. This non-uniform geometry focuses the erase field precisely where needed (over the floating gate) while maintaining simpler structures in other regions. The insulating layer configuration also varies locally to achieve optimal field distribution without requiring complete structural redesign.

Inventive Principle:

Principle #3Local quality

3Reliability

If high voltage is applied to achieve effective erasure, then the erase efficiency improves, but the power consumption and charge pump requirements increase

Engineering Contradiction:

Improveerase efficiencyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The erase gate overhang structure fundamentally changes the electric field distribution parameter, creating a concentrated field that achieves effective erasure at lower voltages. By optimizing the geometric parameters (overhang distance, spacing, insulating layer thickness), the patent achieves enhanced field concentration that reduces the voltage required for successful erasure operations, thereby reducing power consumption and charge pump requirements.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The enhanced dimensional relationship between the erase gate and floating gate reduces the voltage required for erasure, improving erase efficiency and reducing the charge pump requirement, thereby increasing the overall performance of the memory cell.

Implementation Method 1

enhancing the erase efficiency by improving the local electrical field and electron tunneling mechanism

Methodology Applied

Scientific EffectElectron tunneling:

Data Source

PatentUS7927994B1Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

Publication Date: 2011.04.19 SILICON STORAGE TECHNOLOGY INC

AI summary

An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.