Split-Gate Flash Memory With High-K Metal Gate Stack
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Solution Overview
Problem
The increasing complexity of integrated circuit manufacturing due to compact component integration necessitates innovative methods for fabricating high-performance flash memory cells with improved feature sizes and reduced manufacturing complexity.
Innovation Solution
A method for fabricating split-gate flash memory cells using a storage layer with a nitride film interposed between oxide films, a control gate layer, and a protection layer, followed by the formation of high-κ metal gates, which simplifies the process and reduces the thickness of the control gate stack, allowing for more compact and efficient memory cell design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate electrode is replaced with metal gate electrode to improve device performance and achieve feature sizes, then device performance and feature size are improved, but manufacturing process complexity increases
Solution Approach 1:
The gate structure is divided into control gate and floating gate portions, allowing independent formation and optimization of each component. The control gate uses metal electrode for performance while the floating gate uses polysilicon for manufacturability, resolving the contradiction between device performance and manufacturing complexity
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the control gate and floating gate, enabling the combination of metal and polysilicon structures while maintaining electrical isolation and simplifying the overall manufacturing process
2Ease of manufacture
If conventional flash memory fabrication process is used to maintain manufacturing simplicity, then manufacturing process is simpler, but feature size scaling and device performance are limited
Solution Approach 1:
The invention transitions from planar gate structures to three-dimensional stacked gate structures, enabling feature size scaling while maintaining manufacturing simplicity through vertical integration rather than lateral scaling
3Quantity of substance
If control gate stack thickness is increased to improve memory capacity, then flash memory capacity increases, but device area and integration density increase
Solution Approach 1:
The control gate stack is oriented vertically to utilize the third dimension for increasing memory capacity, allowing higher storage density without proportionally increasing the planar device area
Data Source
AI summary
A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-κ metal gate stack disposed on the substrate. The high-κ metal gate stack has a metal gate and a high-κ dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.