Split Gate Flash Memory Integration with Logic Devices
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Solution Overview
Problem
As device geometries shrink, the height of flash memory cells over the substrate surface becomes significantly greater than that of logic devices on the same substrate, leading to leakage and other detrimental effects when attempts are made to shrink both at the same rate.
Innovation Solution
A semiconductor substrate with a recessed memory area and a raised logic device area, where memory cells and logic devices are formed with specific regions and gates, and the substrate height is adjusted through oxidation or epitaxial growth to match the height of logic devices, ensuring comparable top heights for both.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flash memory cell height is reduced at the same rate as logic device geometry shrinkage, then integration density is improved, but leakage and other detrimental effects occur
Solution Approach 1:
The patent introduces a vertical height dimension difference between memory and logic areas by recessing the memory substrate. This allows memory cells to maintain their necessary height for reliable operation while the logic devices remain at the original substrate level, effectively solving the contradiction between integration density and leakage prevention by utilizing the vertical dimension differently across functional areas.
Solution Approach 2:
The patent applies different substrate heights to different functional areas: the memory area has a recessed substrate to accommodate full-height memory cells, while the logic area maintains the original substrate level. This local differentiation allows each area to have the optimal height for its specific function, preventing leakage in memory while maintaining high integration density.
2Reliability
If flash memory cells maintain their height while logic devices are shrunk, then memory cell reliability is preserved, but device integration density deteriorates
Solution Approach 1:
The patent resolves this contradiction by creating a recessed substrate area for memory, allowing memory cells to maintain their full height and reliability while the logic devices in the non-recessed area can be shrunk to increase integration density. The vertical dimension is thus used to differentiate between memory and logic device requirements.
Solution Approach 2:
The substrate is segmented into two distinct regions: a recessed memory area where memory cells maintain full height for reliability, and a non-recessed logic area where devices can be shrunk for higher density. This segmentation allows each region to be optimized independently for its specific function.
3Ease of manufacture
If substrate height is increased to accommodate memory cells, then memory cell formation is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent applies the preliminary action principle by performing oxidation or epitaxial growth on the substrate before forming the memory cells and logic devices. This preliminary height adjustment creates the necessary recessed memory area in advance, simplifying subsequent manufacturing steps by providing a pre-prepared substrate structure that accommodates different device height requirements.
Solution Approach 2:
The patent changes the substrate height parameter through oxidation or epitaxial growth to create a recessed memory area. This parameter change enables memory cell formation with appropriate height while maintaining simpler manufacturing processes, as the height adjustment is achieved through standard semiconductor fabrication techniques rather than complex mechanical or chemical methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of memory cells and logic devices on the same substrate with improved performance and reduced leakage, enhancing the integration and functionality of both components.
Implementation Method 1
performing an oxidation process that forms an oxide layer on the substrate surface in the memory area, wherein the oxidation process consumes and lowers a height of the substrate surface in the memory area
Implementation Method 2
performing an epitaxial growth process that grows silicon on the substrate surface in the logic area, wherein the epitaxial growth process raises a height of the substrate surface in the logic device area
Data Source
Figure 1
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Figure 4~5
AI summary
A memory device comprises a semiconductor substrate with memory (16) and logic device areas (18). A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices are formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.