Split-Gate Flash Memory Manufacturing with Shared Word Line
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Solution Overview
Problem
The challenge in increasing storage density of flash memories is hindered by the limitations of conventional split-gate structures, which require higher programming voltages and result in larger chip sizes, making it difficult to achieve high-density memory cell packing and manufacturing efficiency.
Innovation Solution
A method for manufacturing semiconductor devices with a split-gate structure and MOS transistor that reduces chip size, eliminates 'over-erasure' issues, and increases memory array density by using a specific sequence of dielectric and conductive layer formations, including shallow trench isolation and etch stop layers, to enable efficient programming and erasing while maintaining electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a split-gate structure is adopted to improve programming and erasing performance, then programming efficiency is improved, but chip size increases due to additional word line
Solution Approach 1:
The patent implements a shared word line structure where a single word line serves dual purposes: controlling memory cells in the first array and controlling memory cells in the second array. This nesting of control functions within a single structural element eliminates the need for separate word lines for each array, thereby reducing chip size while maintaining the programming efficiency benefits of split-gate structures.
Solution Approach 2:
The word line is designed with multi-functionality to control memory cells across different arrays simultaneously. By making the word line universal rather than dedicated to a single array, the structure achieves space efficiency without sacrificing the operational advantages of split-gate configuration.
2Quantity of substance
If memory cell density is increased by forming more memory cells in the wafer, then storage density is improved, but manufacturing difficulty increases due to extremely fine lines required in masking and etching processes
Solution Approach 1:
The patent addresses manufacturing challenges by transitioning from two-dimensional scaling to three-dimensional structure formation. The shallow trench isolation and multi-layer conductive structures enable vertical differentiation that relaxes the requirements for extreme lateral line precision, allowing high density to be achieved through vertical stacking and spatial arrangement rather than solely through reducing lateral dimensions.
3Area of stationary object
If chip size is reduced to increase storage density, then area is reduced, but programming voltage requirements become more difficult to meet
Solution Approach 1:
The patent divides the memory structure into distinct regions with shallow trench isolation separating first and second device regions. This segmentation allows independent optimization of electrical characteristics in each region, enabling reduced chip size while maintaining adequate programming voltage through controlled electrical isolation and targeted voltage application in segmented areas.
Data Source
AI summary
A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.