Self-Aligned Split Gate Flash Memory Void Prevention
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Solution Overview
Problem
The existing methods for fabricating split gate flash memory cells often result in void formation during the recessing of memory gate precursors, leading to potential damage during subsequent etching steps and affecting the reliability of the integrated circuit.
Innovation Solution
The approach involves lowering the memory gate material before forming dielectric spacers, using the memory gate spacer as a mask, and then forming a dielectric liner along the sidewalls, which prevents void formation and enhances reliability by exposing the memory gate surface during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory gate precursor is recessed to form memory gate, then memory gate structure is formed, but voids form over the memory gate causing reliability issues
Solution Approach 1:
The patent performs the recessing operation to form the memory gate before forming the dielectric spacer, rather than after. This preliminary action allows the dielectric spacer to be formed in a planar region, preventing void formation during subsequent etching steps while still achieving the desired memory gate structure
Solution Approach 2:
The patent segments the fabrication process into distinct stages: first forming the memory gate by recessing the memory gate precursor, then forming the dielectric spacer in a separate step. This segmentation allows each operation to be optimized independently, preventing the void formation issue that occurs when operations are combined or performed in reverse order
2Manufacturing precision
If dielectric spacer is formed after memory gate precursor recessing, then memory gate is defined, but small recess causes void formation during etching
Solution Approach 1:
The patent performs the recessing operation to form the memory gate before forming the dielectric spacer, rather than after. This preliminary action allows the dielectric spacer to be formed in a planar region, preventing void formation during subsequent etching steps while still achieving the desired memory gate structure
Solution Approach 2:
The patent introduces a dielectric liner as an intermediary layer between the memory gate and the dielectric spacer. This dielectric liner fills the recess region and provides a planar surface for dielectric spacer formation, eliminating the void formation problem while maintaining precise memory gate definition
Data Source
AI summary
The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has a memory gate with a flat top surface. A memory gate spacer is arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate. The memory gate spacer has an inner sidewall disposed along an upper portion of a charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate. In some embodiments, a dielectric liner is continuously lined the outer sidewall of the memory gate, extending on a portion of the top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer.