Split-Gate Flash Memory Cell Read Window Optimization
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Solution Overview
Problem
Split-gate flash memory cells face challenges in optimizing read performance, particularly in distinguishing between programmed and erased states due to limited read window and asymmetry issues caused by manufacturing tolerances.
Innovation Solution
Applying a non-zero voltage to the control gate terminal during read operations to selectively improve either the programmed or erased state read performance, with different voltage values set based on intended usage and performance characteristics, and stored in trim bits for individual memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read operation with zero control gate voltage is used, then device complexity is minimized, but read performance and read window are limited
Solution Approach 1:
The patent applies parameter changes by varying the control gate voltage (VCG) during read operations to optimize read performance. Different voltage values are applied depending on whether the cell is in programmed or erased state, allowing the system to adapt the electrical parameters dynamically to achieve better read window and distinguishability between states without fundamentally changing the device structure.
2Ease of manufacture
If manufacturing tolerances are present, then ease of manufacture is improved, but asymmetry between even and odd rows degrades read performance
Solution Approach 1:
The patent addresses manufacturing-induced asymmetry by applying different control gate voltages to even and odd rows during read operations. This asymmetric voltage application compensates for the physical asymmetries introduced during manufacturing, restoring symmetry in read performance across all rows without requiring tighter manufacturing tolerances.
3Reliability
If control gate voltage is applied during read operations, then read window and read performance are improved, but energy consumption increases
Solution Approach 1:
The patent applies partial action by using minimal control gate voltage adjustments rather than full voltage swings. The VCG is biased to small positive or negative values sufficient to improve read window and distinguishability, avoiding excessive voltage application that would unnecessarily increase energy consumption while still achieving the desired performance improvement.
Data Source
AI summary
Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage VCGR to the control gate.