Split Gate Isolation Fill Using Low-k Dielectrics to Cut Fringing Capacitance
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Solution Overview
Problem
The formation of long gate structures in integrated circuits, when patterned into shorter sections, leads to undesirable fringing capacitance due to the use of high dielectric constant materials like silicon nitride for isolation, which affects device performance by increasing delay times in ring oscillators and altering threshold voltages.
Innovation Solution
Partially replacing silicon nitride with a lower-k dielectric material and introducing air-gaps or seams in the dielectric fill structure to reduce the effective dielectric constant, achieved by depositing a silicon nitride liner followed by a silicon oxide or silicon oxy-carbide fill material, which has a dielectric constant equal to or less than 3.9, and adjusting the deposition process to form controlled air-gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride is used to fill the space formed by removed gate structure portions, then the isolation between transistor gates is improved, but fringing capacitance increases causing increased delay time and altered threshold voltage
Solution Approach 1:
The patent changes the dielectric constant parameter of the fill material from high-k silicon nitride (k≈7.5) to lower-k materials such as silicon oxide (k≈3.9) or silicon oxy-carbide (k<3.9). This parameter change directly reduces fringing capacitance while maintaining adequate gate isolation, thereby resolving the contradiction between isolation quality and harmful capacitance effects.
Solution Approach 2:
The patent employs composite dielectric structures combining silicon nitride liners with lower-k silicon oxide or silicon oxy-carbide fill materials. The silicon nitride liner provides protective functions while the lower-k bulk material reduces fringing capacitance. This composite approach maintains the protective properties of silicon nitride while eliminating the harmful high-k capacitance effects.
2Object-generated harmful factors
If air-gaps or seams are introduced in the dielectric fill structure, then fringing capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent controls the deposition parameters (thickness, conformality, and discontinuity) of the dielectric fill material to create air-gaps or seams. By adjusting these parameters during deposition, the process forms controlled discontinuities in the fill structure that reduce fringing capacitance without requiring additional process steps, thus managing complexity while achieving the desired electrical effect.
3Object-generated harmful factors
If lower-k dielectric material is used to reduce fringing capacitance, then delay time and threshold voltage are improved, but protective properties against oxygen diffusion may be reduced
Solution Approach 1:
The patent creates a composite structure where a thin silicon nitride liner provides the protective barrier against oxygen diffusion, while the bulk lower-k silicon oxide or silicon oxy-carbide material provides the low-fringing-capacitance environment. This composite approach allows each material to perform its optimal function: silicon nitride for protection and lower-k material for capacitance control.
Solution Approach 2:
The patent applies different dielectric materials to different regions of the fill structure. The silicon nitride liner is applied locally at critical interfaces where oxygen diffusion protection is needed, while the lower-k material fills the bulk region where capacitance reduction is the primary concern. This local differentiation allows simultaneous achievement of protective and electrical performance goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces fringing capacitance, improving the performance of integrated circuits by minimizing the impact on threshold voltage and delay times, while maintaining the protective properties of the dielectric material.
Implementation Method 1
depositing silicon oxide or a silicon oxide based dielectric, such as silicon oxy-carbide, that has a dielectric constant equal to or less than 3.9
Implementation Method 2
adjusting the deposition process to form controlled air-gaps
Data Source
AI summary
The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.