Split Gate Memory Cell Asymmetric Height Design
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Solution Overview
Problem
Existing manufacturing techniques for split gate non-volatile memory cells face challenges in efficiently forming the control and select gates while minimizing leakage and ensuring effective charge storage, particularly with nanocrystals, which can be adversely impacted by etching processes.
Innovation Solution
The method involves forming the select gate first, followed by the control gate, with the control gate being recessed to a lower height than the select gate, and using a sidewall spacer to prevent silicide bridging, allowing for full silicidation of the select gate and minimizing the impact on nanocrystals used for charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control gate and select gate are formed at the same height, then the manufacturing process is simpler, but leakage occurs and programming efficiency is reduced
Solution Approach 1:
The patent applies asymmetry by forming the control gate and select gate at different heights. Specifically, the control gate is recessed relative to the select gate, creating an asymmetric structure where the select gate protrudes higher. This height difference prevents leakage paths while maintaining manufacturing feasibility through selective etching processes.
Solution Approach 2:
The patent transitions from a two-dimensional planar gate structure to a three-dimensional vertical structure by recessing the control gate below the select gate level. This vertical dimensioning creates distinct electrical isolation zones and prevents leakage without requiring additional lateral space or complex planar layouts.
2Reliability
If the control gate is fully silicided to reduce resistance, then conductivity improves, but nanocrystals are damaged by etching processes
Solution Approach 1:
The patent applies preliminary action by forming the control gate recess before performing silicidation on the select gate. This sequence allows the control gate area to be prepared and protected in advance, enabling subsequent silicidation processes to be applied selectively only to the select gate without exposing nanocrystals to damaging etchants.
Solution Approach 2:
The patent applies local quality by differentiating the treatment of different gate regions. The control gate region maintains its original material composition without silicidation to protect nanocrystals, while the select gate receives full silicidation treatment to achieve low resistance. This localized differentiation optimizes both conductivity and nanocrystal preservation.
3Reliability
If the select gate is formed first to enable proper charge storage, then charge storage efficiency improves, but subsequent control gate formation becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the gate formation process into distinct sequential stages: first forming the select gate with charge storage layer, then separately forming the recessed control gate. This segmentation allows each gate structure to be optimized independently while maintaining overall manufacturing feasibility through modular processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces failures due to leakage, enhances programming efficiency, and simplifies subsequent processing steps by maintaining low topography, ensuring high select gate conductivity and efficient read operations while protecting charge storage nanocrystals.
Implementation Method 1
a sidewall spacer is formed from the select gate to the control gate
Implementation Method 2
Both the control gate and the select gate are silicided but there is no bridging of the silicide between them
Data Source
AI summary
A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.