Split-Gate Memory Cell Over-Programming Error Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND flash memory devices, over-programmed memory cells can lead to inaccurate data state determination due to threshold voltage variations, causing errors in read and verify operations, especially when some cells remain deactivated despite being programmed, as they do not respond to the pass voltage applied to their control gates.
Innovation Solution
The implementation of split-gate memory cells with an assist memory cell portion that is programmed to a controlled range of threshold voltages, allowing for accurate data state detection by ensuring that only the primary memory cell portion's activation determines the current flow, thereby mitigating over-programming errors and improving programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single control gate is used in traditional NAND flash memory cells, then the device complexity is reduced, but over-programming errors occur causing inaccurate data state determination
Solution Approach 1:
The control gate is divided into two separate control gates (first control gate and second control gate) that can be independently controlled. This segmentation allows selective activation of memory cell portions during read operations, enabling accurate detection of target memory cells while preventing over-programmed cells from causing errors, thus resolving the contradiction between reliability and device complexity.
2Productivity
If pass voltage is applied to activate remaining memory cells during sensing, then read operation speed is improved, but over-programmed cells remain deactivated causing sensing errors
Solution Approach 1:
Different voltage levels are applied to different control gates based on local requirements: the first control gate receives a pass voltage to activate non-target memory cells for fast reading, while the second control gate receives a selective voltage that activates only properly programmed target cells. This local quality differentiation enables both high read speed and accurate sensing by addressing different functional requirements in different parts of the system.
3Reliability
If multiple programming pulses are used to ensure proper programming, then programming reliability is improved, but programming time and power consumption increase
Solution Approach 1:
The split-gate structure provides inherent feedback capability where the second control gate can be used to verify programming status during the programming process. By monitoring the state of memory cells through the second control gate, the system can determine when programming is complete and stop further pulsing, thereby maintaining high programming reliability while significantly reducing programming time and power consumption compared to traditional multi-pulse approaches.
Data Source
AI summary
Memories might include an array of memory cells including a string of series-connected split-gate memory cells, and a controller configured to cause the memory to selectively activate a first memory cell portion of a selected split-gate memory cell of the string of series-connected split-gate memory cells in response to a data state of the first memory cell portion of the selected split-gate memory cell and deactivate a second memory cell portion of the selected split-gate memory cell, and activate a second memory cell portion of each remaining split-gate memory cell of the string of series-connected split-gate memory cells while selectively activating the first memory cell portion of the selected split-gate memory cell and deactivating the second memory cell portion of the selected split-gate memory cell.