Split-Gate 2-Bit Memory Cell With Stacked Erase and Word Line Gates
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Solution Overview
Problem
Existing split-gate non-volatile memory cells face complexity and performance limitations due to multiple electrodes and channel regions, with configurations lacking efficient erase gates and high coupling ratios, which complicates their architecture and array layout as critical dimensions shrink.
Innovation Solution
A 2-bit memory cell design featuring a continuous channel region with a word line gate and an erase gate disposed over the word line gate, along with floating and coupling gates, allowing for simplified architecture and enhanced erase efficiency through a method that includes forming insulation layers and conductive layers on a semiconductor substrate, with the erase gate positioned vertically and insulated from the word line gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple electrodes and separate channel regions are used in split-gate memory cells, then memory functionality is achieved, but device complexity and array layout complexity increase significantly
Solution Approach 1:
The patent merges two separate channel regions into a single continuous channel region that extends between source and drain regions. This continuous channel is controlled by a common word line gate, eliminating the need for separate channel regions and reducing the number of electrodes required. The merging of channel regions directly reduces device complexity while maintaining memory functionality through the split-gate configuration with floating gates.
Solution Approach 2:
The common word line gate serves multiple functions by controlling the single continuous channel region for both memory cells in the pair. This universal gate structure eliminates the need for separate control gates for each channel region, reducing the number of electrodes and simplifying the array layout while maintaining the ability to control both memory cells.
2Device complexity
If erase gates are eliminated to simplify structure, then device complexity reduces, but erase efficiency and performance are compromised
Solution Approach 1:
The erase gate is nested vertically over the word line gate, creating a stacked configuration where the erase gate is positioned directly above the word line gate. This nesting arrangement allows the erase gate to be integrated into the existing gate structure without adding horizontal complexity, while still providing the necessary erase functionality through vertical stacking.
Solution Approach 2:
The patent transitions from a planar arrangement of gates to a vertical stacking configuration. The erase gate is positioned in the vertical dimension over the word line gate, allowing both gates to coexist without increasing horizontal footprint. This dimensional change enables erase functionality to be added without proportionally increasing overall device complexity.
3Productivity
If critical dimensions are reduced to increase storage density, then productivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes vertical stacking of the erase gate over the word line gate to increase storage density without proportionally reducing critical dimensions in the plane. By moving functionality to the vertical dimension, the design achieves higher density while maintaining manufacturable critical dimensions, as the vertical stacking can be formed using standard deposition and etching processes.
Data Source
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AI summary
A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate.