Split Gate Memory Cell Fabrication via Wet Etch
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Solution Overview
Problem
The thinning of access gate oxide in split-gate flash memory cells leads to programming disturb mechanisms, where charge leakage can unintentionally alter the data state, causing errors in binary states (0 to 1 or 1 to 0) due to intrinsic and extrinsic factors like gate oxide leakage and substrate damage during etching.
Innovation Solution
A method for forming integrated circuits with varying dielectric layers of different thicknesses on a semiconductor substrate, where a thick dielectric layer is formed first, followed by a medium-thickness layer, and then a thin dielectric layer is grown without plasma etching, reducing the risk of charge leakage and substrate damage by using a wet etch to create the thin oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the access gate oxide thickness is reduced to enable scaling, then the memory cell can be scaled down and integrated at higher densities, but the thinner oxide becomes vulnerable to charge leakage and programming disturb that can unintentionally alter data state
Solution Approach 1:
The patent segments the gate oxide structure into multiple layers with different thicknesses: a thinner access gate oxide for scaling and a thicker floating gate oxide for stable charge storage. This segmentation allows each layer to fulfill its specific function while mitigating the drawbacks of thinning the overall structure.
Solution Approach 2:
The patent applies local quality by creating regions with different oxide thicknesses in specific locations. The access gate region has thinner oxide for scaling, while the floating gate region maintains thicker oxide for reliability, allowing local optimization of each component's properties.
2Productivity
If plasma etching is used to remove dielectric layers during fabrication, then the manufacturing process is efficient and controllable, but the etching process causes damage to the semiconductor substrate that creates vulnerability to charge leakage
Solution Approach 1:
The patent extracts or removes the harmful plasma etching step from the fabrication process and replaces it with a wet chemical etching process. This elimination of the harmful element (plasma) while maintaining the functional requirement (dielectric removal) resolves the contradiction between productivity and substrate damage.
Solution Approach 2:
The patent uses a sacrificial dielectric layer that is intentionally created and then completely removed by wet etching. This disposable layer protects the substrate during fabrication and is discarded after serving its purpose, avoiding the need for damaging plasma etching of the final structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of programming disturbs by minimizing charge injection and substrate damage, ensuring accurate data storage and retrieval in split-gate flash memory cells while concurrently forming dielectric layers for other devices on the same substrate.
Implementation Method 1
The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area
Implementation Method 2
thereafter growing the first dielectric layer in the first substrate area and the second substrate area
Data Source
AI summary
A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.