Split Gate NVM Cell Integration with Logic Devices
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Solution Overview
Problem
The integration of non-volatile memory (NVM) transistors with logic transistors is challenging due to different requirements, particularly at small gate lengths, where NVMs using control gates over floating gates are unreliable, and high-k gate dielectric is needed to reduce leakage effects.
Innovation Solution
The method involves forming split gate non-volatile memory cells with a select gate and a control gate, using layers of oxide and nitride over a semiconductor substrate, and depositing a high-k gate dielectric over the logic device region, with an interlayer dielectric polished to form a spacer control gate, allowing for integration with logic devices using the same processing technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control gate over floating gate configuration is used for NVM, then charge storage capability is improved, but reliability deteriorates at small gate lengths (28 nanometers or less)
Solution Approach 1:
The patent changes the gate configuration from a single control gate to a split gate structure with select gate and control gate portions, and modifies the charge storage layer from continuous to discontinuous nanocrystals. These parameter changes enable reliable operation at scaled gate lengths of 28 nanometers or less while maintaining charge storage capability.
Solution Approach 2:
The patent employs a composite structure combining oxide layers, nitride layers, and nanocrystal charge storage elements within the memory cell, integrated with high-k gate dielectric in the logic region. This composite material approach enables simultaneous achievement of reliable NVM operation and compatibility with scaled logic device requirements.
2Adaptability or versatility
If traditional NVM structures are integrated with logic transistors, then memory functionality is achieved, but manufacturing complexity increases due to different processing requirements
Solution Approach 1:
The patent creates a unified fabrication process that can manufacture both NVM cells and logic devices using the same processing technology. The split gate NVM structure and logic device share common fabrication steps, including oxide and nitride layer deposition, nanocrystal formation, and etching processes, eliminating the need for separate specialized processing lines.
Solution Approach 2:
The patent segments the gate structure into select gate and control gate portions, and divides the charge storage layer into discontinuous nanocrystals. This segmentation allows different regions to be optimized for their specific functions while being fabricated using the same overall process flow, reducing manufacturing complexity.
3Speed
If gate dielectric thickness is scaled below 2 nanometers for high-speed logic operation, then speed is improved, but leakage effects increase
Solution Approach 1:
The patent introduces high-k gate dielectric material in the logic device region, which has a higher dielectric constant than traditional silicon dioxide. This allows the gate dielectric to be physically thicker while providing equivalent or superior electrical isolation, thereby reducing leakage effects while maintaining high-speed operation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable integration of NVM and logic devices at scaled gate lengths of 28 nanometers or less, ensuring efficient charge storage and high-speed operation by using nanocrystals as charge storage elements within a shared processing technology.
Implementation Method 1
high-k gate dielectric is needed to reduce leakage effects as gate dielectric thickness scales below 2 nanometers
Implementation Method 2
NVM with nanocrystals are a more viable option as gate lengths decrease
Data Source
AI summary
A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.