Split-Gate Non-Volatile Memory With Sharp Tunneling Dielectric
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Solution Overview
Problem
Thin tunneling dielectric layers in split-gate non-volatile memory cells cause current leakage, leading to poor data retention and large memory cell sizes, which are not suitable for miniaturization.
Innovation Solution
A non-volatile memory design featuring a floating gate with sharp portions and a tunneling dielectric layer that is thicker due to the inclusion of sharp depression portions, preventing current leakage and enhancing data retention, while maintaining a compact device size through a split-gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a thin tunneling dielectric layer is used to enable quick erase with low power, then erase efficiency is improved, but current leakage increases causing poor data retention
Solution Approach 1:
The patent applies different dielectric materials with different properties to different regions of the gate structure. Specifically, a first dielectric material (e.g., silicon oxide) is used in the tunneling region where thin thickness is needed for erase efficiency, while a second dielectric material (e.g., silicon nitride or silicon oxynitride) with higher breakdown strength is used in the isolation region to prevent leakage. This local differentiation allows the structure to simultaneously achieve quick erase and good data retention.
2Reliability
If a thick tunneling dielectric layer is used to prevent current leakage, then data retention is improved, but erase efficiency decreases
Solution Approach 1:
The patent divides the dielectric layer into functionally distinct regions: a thin tunneling dielectric portion (first dielectric material) that enables efficient charge injection during erase operations, and a thicker isolation dielectric portion (second dielectric material) that prevents leakage and maintains data retention. This local quality differentiation allows each region to optimize for its specific function.
3Area of stationary object
If a split-gate structure is used to reduce memory cell size, then device miniaturization is achieved, but current leakage increases due to thin dielectric requirements
Solution Approach 1:
The split-gate structure utilizes a first dielectric material in the tunneling path between floating gate and erasing gate to enable thin thickness for compact design and quick erase, while employing a second dielectric material in the isolation region to provide high breakdown strength and prevent leakage. This material differentiation allows the compact split-gate structure to maintain both small size and high reliability.
4Reliability
If independent transistors are designed to enhance tunneling effect, then data retention is improved, but memory cell size increases
Solution Approach 1:
The patent merges the word line and erasing gate functions into a single integrated structure, eliminating the need for two independent transistors. The combined structure includes a gate dielectric layer and conductive layer that serve both as the word line for reading operations and as the erasing gate for data erase operations, thereby reducing memory cell area while maintaining tunneling effectiveness through the differentiated dielectric materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents current leakage, improves data retention, and enhances programming and erase efficiency by increasing the thickness of the tunneling dielectric layer, while reducing memory cell size, thus addressing the limitations of prior art.
Implementation Method 1
a tunneling dielectric layer between a floating gate and an erasing gate is usually thin as the tunneling effect between the floating gate and the erasing gate is restricted
Data Source
AI summary
The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.