Split-Gate Memory Cell Layout With Self-Aligned Floating Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As split gate non-volatile memory cells are scaled down in size, manufacturing challenges arise due to component misalignment and increased complexity, leading to performance variances and difficulties in forming memory cells on substrates with logic devices.
Innovation Solution
A method involving the formation of shallow trench isolation regions, followed by the creation of insulation and conductive spacers to define source and drain regions, and the use of oxide spacers to dictate the size and position of floating gates, allowing for uniformity and efficient erase performance with fewer masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If split gate memory cells are scaled down in size, then memory density increases, but manufacturing precision deteriorates due to component misalignment and channel length variances
Solution Approach 1:
The patent applies preliminary action by forming the floating gate structure before defining the control gate position. The floating gate is formed first in the channel region, then the control gate is subsequently positioned relative to it. This sequence ensures that the control gate aligns properly with the floating gate, preventing misalignment issues that would otherwise worsen with scaling.
Solution Approach 2:
The patent employs self-service through self-aligned fabrication processes where previously formed structures serve as alignment references for subsequent steps. The floating gate structure formed earlier automatically defines the position for the control gate, eliminating the need for separate alignment operations and thereby maintaining precision despite scaling.
2Manufacturing precision
If additional masking steps are introduced to achieve desired component dimensions, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into fewer fabrication steps. The control gate formation process simultaneously achieves both the positioning of the control gate relative to the floating gate and the definition of the channel region boundaries. This consolidation reduces the total number of masking steps while maintaining the necessary dimensional precision.
Solution Approach 2:
The patent applies universality by designing the control gate structure to serve multiple purposes: it acts as both the control electrode for the memory cell and as an alignment reference for subsequent fabrication steps. This multi-functionality eliminates the need for separate alignment markers or additional masking steps, reducing overall process complexity.
3Productivity
If memory cells are formed on substrates with logic devices, then substrate utilization improves, but manufacturing precision deteriorates due to mixed device requirements
Solution Approach 1:
The patent applies local quality by implementing device-specific parameter optimization. Different regions of the substrate can have tailored floating gate depths, control gate dimensions, and oxide thicknesses according to whether they contain memory cells or logic devices. This localized customization allows high-density memory formation while maintaining compatibility with logic device requirements on the same substrate.
Solution Approach 2:
The patent segments the substrate into distinct memory cell regions and logic device regions, each with optimized fabrication parameters. The memory regions use parameters optimized for high-density storage while logic regions use parameters optimized for device performance. This segmentation allows both device types to coexist on the same substrate without compromising the precision of either.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniformity in floating gate and control gate spacing, improves erase efficiency, and simplifies the manufacturing process by reducing the number of masking and processing steps, enabling reliable scaling of split gate memory cells concurrently with logic devices.
Implementation Method 1
The floating gate 20 is insulated from the substrate 12 by an oxide layer 24
Implementation Method 2
electrons on the floating gate 20 to tunnel through an intermediate insulation 26 (e.g., tunnel oxide) from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling
Implementation Method 3
Some of the heated electrons will be injected through the oxide 24 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20
Implementation Method 4
Some of the heated electrons will be injected through the oxide 24 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.