Split-Gate Flash Source Structure for Low Rs Cell Shrinkage
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Solution Overview
Problem
Split-gate flash memory cell devices face a trade-off between reducing source resistance (Rs) and achieving cell shrinkage capability, as heavily doped source lines increase junction depth and width, adversely affecting channel regions.
Innovation Solution
A semiconductor structure for a memory device is developed, featuring a source structure with an epitaxial layer and an underlying doped region, where the epitaxial layer is heavily doped and confined between gate structures, reducing Rs while improving cell shrinkage capability without junction depth and width issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heavily doped source lines are used to reduce source resistance, then source resistance is reduced, but junction depth and width increase adversely affecting channel regions
Solution Approach 1:
The source line is divided into two distinct segments: a heavily doped epitaxial source region (first conductivity type) and an underlying lightly doped substrate source region (second conductivity type). This segmentation allows each region to serve different functions - the heavily doped epitaxial region reduces source resistance while the lightly doped substrate region limits junction depth and width, thereby resolving the technical contradiction between reducing source resistance and controlling junction dimensions.
2Productivity
If cell shrinkage is achieved to improve device density, then device density increases, but source resistance control becomes more difficult
Solution Approach 1:
Different regions of the source structure are assigned different doping qualities - the epitaxial source region is heavily doped to reduce source resistance, while the substrate source region is lightly doped to control junction depth. This local differentiation of doping quality allows the source structure to simultaneously achieve low source resistance and maintain proper electrical characteristics even as device dimensions are reduced for higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces source resistance and enhances cell shrinkage capability, improving the performance of split-gate flash memory cell devices by using an epitaxial layer and doped region to manage junction depth and width.
Implementation Method 1
An epitaxial source region (first conductivity type) is formed to fill the recess. The epitaxial source region is heavily doped
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.