Split Ladder Acoustic Resonator Filter With Separate Series-Shunt Chips
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Solution Overview
Problem
Conventional RF filters using acoustic wave resonators face challenges in achieving optimal performance across various parameters like insertion loss, rejection, isolation, power handling, and cost, due to the need for a single material stack that meets the different requirements of series and shunt resonators, which can lead to suboptimal design and increased complexity.
Innovation Solution
The implementation of a split ladder filter design, where series and shunt resonators are fabricated on separate chips with distinct material stacks, allowing for separate optimization and improved performance by exploiting different material properties for each type of resonator, thereby reducing spurious modes and enhancing filter bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single material stack is used for both series and shunt resonators, then device complexity is reduced, but performance optimization is limited due to conflicting requirements
Solution Approach 1:
The filter is divided into two separate modules: a first module containing series resonators with a first material stack optimized for series resonator requirements, and a second module containing shunt resonators with a second material stack optimized for shunt resonator requirements. This segmentation allows each material stack to be independently optimized without compromise, resolving the contradiction between device complexity and performance reliability.
2Reliability
If separate material stacks are used for series and shunt resonators, then performance optimization is improved, but device complexity increases
Solution Approach 1:
The first and second modules are combined into a single integrated filter device with unified packaging and interconnections. The series resonators in the first module are electrically connected to the shunt resonators in the second module through conductive paths within the same device housing, merging the two separately optimized material stacks into a functional whole that achieves high performance without excessive complexity.
3Ease of manufacture
If conventional single-module design is used, then manufacturing is simpler, but spurious modes increase and bandwidth is reduced
Solution Approach 1:
By segmenting the filter into separate modules with distinct material stacks, each module can be manufactured and optimized independently to minimize spurious modes. The first material stack is specifically designed to reduce spurious modes in series resonators, while the second material stack addresses spurious modes in shunt resonators, achieving higher manufacturing precision without significantly increasing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables better temperature stability and reduced power dissipation, meeting specific insertion loss requirements and improving overall filter performance across various frequency bands, such as LTE Band 2, while also offering cost-effective solutions for portable devices.
Implementation Method 1
The resonator includes a piezoelectric material between the first electrode and the second electrode
Implementation Method 2
transversely-excited bulk acoustic resonator
Data Source
AI summary
Filter devices. A first chip includes a first interdigital transducer (IDT) of a first acoustic resonator formed on a surface of a first piezoelectric wafer having a first thickness, interleaved fingers of the first IDT disposed on a portion of the first piezoelectric wafer spanning a first cavity in a first base. A second chip includes a second IDT of a second acoustic resonator formed on a surface of a second piezoelectric wafer having a second thickness less than the first thickness, interleaved fingers of the second IDT disposed on a portion of the second piezoelectric wafer spanning a second cavity in a second base. A circuit card coupled to the first chip and the second chip includes at least one conductor for making an electrical connection between the first IDT and the second IDT.