Split Trench Gate Semiconductor Layout for Stable Emitter Connection

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Solution Overview

Problem

In semiconductor devices with a split gate structure, defects in contact hole formation can lead to a floating potential in embedded electrodes, resulting in a withstand voltage defect due to incomplete connection between the gate split part and the emitter electrode.

Innovation Solution

A semiconductor device design featuring a two-stage trench gate structure with a gate intersection trench gate that connects all first gate electrodes, ensuring stable electrical connection to the emitter potential and reducing withstand voltage defects by providing a common potential to all embedded electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a contact hole is provided to only one of two active trenches to connect the gate split part and emitter electrode, then the device complexity is reduced, but the reliability deteriorates due to potential floating potential and withstand voltage defects

Engineering Contradiction:
Improvestructure complexityVSAvoidconnection stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by providing contact holes at specific locations (both active trenches) rather than uniformly across all trenches. The gate intersection trench gate is positioned specifically in the electrode extraction region to connect first gate electrodes, creating localized connection points that ensure reliability without unnecessary complexity.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple contact holes are provided in different active trenches to ensure stable connection, then the reliability is improved, but the device complexity increases

Engineering Contradiction:
Improveconnection stabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate intersection trench gate serves multiple functions: it connects first gate electrodes to each other, provides a pathway for electrical connection to the emitter potential, and is formed in the electrode extraction region to facilitate reliable connectivity. This multi-functional design reduces the need for separate dedicated connection structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If the gate intersection trench gate is provided to connect all first gate electrodes, then the manufacturing precision is improved by ensuring complete electrical connection, but the device complexity increases

Engineering Contradiction:
Improveelectrical connection completenessVSAvoidgate structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate structure is segmented into first gate electrodes (in active trenches) and a gate intersection trench gate (in the electrode extraction region). This segmentation allows each component to be formed and connected independently, ensuring that all first gate electrodes are reliably connected to the emitter potential through the intersection trench gate without requiring a single complex continuous structure.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240178305A1Semiconductor device
Publication Date: 2024.05.30 MITSUBISHI ELECTRIC CORP
  • US20240178305A1 patent drawing
  • US20240178305A1 patent drawing
  • US20240178305A1 patent drawing

AI summary

A semiconductor device according to the present disclosure includes: a semiconductor substrate including at least: an n-type first semiconductor layer; an n-type second semiconductor layer on the first semiconductor layer; a p-type third semiconductor layer on the second semiconductor layer; and an n-type fourth semiconductor layer on an upper layer part of the third semiconductor layer; a plurality of first trench gates passing through the fourth to second semiconductor layers to reach an inner side of the first semiconductor layer; and a first main electrode having contact with the fourth semiconductor layer; wherein the plurality of first trench gates are disconnected in an electrode extraction region provided in a center part of the active region where main current flows, and are connected to the first main electrode in a first electrode extraction part connected to the first gate electrode in the disconnected part.