Split Trench Gate Layout for Fast Switching and Withstand Voltage
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Solution Overview
Problem
Existing semiconductor devices with trench gate structures face challenges in balancing switching speed and withstand voltage, with prior art not effectively addressing the trade-off between these two performance metrics.
Innovation Solution
The semiconductor device incorporates a split gate structure with specific arrangements of gate trenches, field plate trenches, and electrodes, including a field plate trench between gate trenches, to enhance channel area and reduce on-resistance while alleviating electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a trench gate structure is used to improve switching speed, then switching speed is improved, but withstand voltage decreases
Solution Approach 1:
The gate structure is segmented into multiple gate trenches arranged in parallel, each contributing to the overall gate control. This segmentation allows the electric field to be distributed across multiple trenches rather than concentrated in a single deep trench, improving both switching speed and withstand voltage characteristics
Solution Approach 2:
The invention transitions from a conventional single deep trench gate to a multi-dimensional arrangement of multiple shallower gate trenches. By adding the horizontal dimension with multiple parallel trenches, the device achieves improved switching speed through better gate control while maintaining withstand voltage through distributed electric field management
2Reliability
If the channel area is increased to reduce on-resistance, then on-resistance is reduced, but device complexity increases
Solution Approach 1:
The channel region is segmented into multiple parallel current paths defined by adjacent gate trenches. This segmentation increases the total effective channel area and reduces on-resistance while maintaining a relatively simple fabrication process using standard trench isolation and gate electrode deposition techniques
Solution Approach 2:
Multiple gate trenches and their associated channel regions are merged into a single integrated device structure with shared source and drain regions. This merging approach increases the effective channel area for current flow while avoiding the complexity of completely separate device structures
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes: a first gate trench and a second gate trench, arranged along a first direction in a plan view seen from a direction perpendicular to the upper surface, and extending along a second direction intersecting the first direction; a third gate trench, extending along the first direction from the first gate trench toward the second gate trench and forming a first gap with the second gate trench; a fourth gate trench, spaced apart from the third gate trench along the second direction, extending along the first direction from the second gate trench toward the first gate trench and forming a second gap with the first gate trench; a field plate trench, disposed in a cell region surrounded by the first to fourth gate trenches; and gate electrodes, disposed within the first to fourth gate trenches.