Split Via Layout for Dense PCB Routing and Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional via design in semiconductor devices results in significant via land footprints, leading to congested circuit board areas, limited routing spaces, and irregular trace designs, particularly affecting high-speed data transfer and power signal plane design.
Innovation Solution
Implementing a split via structure with half-moon shaped via lands and vias, allowing for reduced via land footprints and optimized trace connections, including differential pair and power signal transmission configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via design is used, then via connections are established, but via land footprints become large causing circuit board congestion
Solution Approach 1:
The via structure is segmented into two separate via lands instead of one large circular via land. Each via land has a reduced footprint and contains a via, with the two via lands positioned adjacent to each other. This segmentation allows the same electrical connection function to be achieved while significantly reducing the overall area occupied on the circuit board, thereby resolving the contradiction between reliable via connection and minimal via land footprint.
2Reliability
If conventional via design is used, then via connections are established, but routing spaces become limited and trace designs become irregular
Solution Approach 1:
By dividing the conventional single via land into two smaller via lands, the routing space around each via land becomes more available. The smaller footprint of each via land creates additional clearance for trace routing, allowing for more regular and optimized trace designs. This segmentation approach maintains reliable via connections while increasing the complexity of the via structure to benefit routing flexibility.
3Area of stationary object
If via placement is tightened, then circuit board congestion is reduced, but trace length matching becomes more difficult
Solution Approach 1:
The two via lands are positioned asymmetrically relative to the traces they serve. This asymmetric positioning allows for optimized trace routing where trace length matching can be achieved more easily. The via lands can be placed at different distances and orientations from their respective traces, enabling precise control over trace lengths even when via placement is tightened, thus resolving the contradiction between reduced congestion and maintained manufacturing precision.
Data Source
AI summary
A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.


