SRAM Standby Current Reduction via Back Gate Biasing
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Solution Overview
Problem
Conventional SRAMs do not sufficiently reduce standby current, despite efforts to minimize power supply voltage for peripheral circuits during standby.
Innovation Solution
A semiconductor memory device utilizing first and second power supply voltages, where the second power supply voltage is shut off during standby, and a P-channel MOS transistor with a back gate receiving the first power supply voltage is used in the write/read circuit, along with a pull-up circuit to maintain the transistor out of conduction, ensuring a low standby current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the second power supply voltage for the peripheral circuit is shut off during standby, then standby current is reduced, but the threshold voltage of the P-channel MOS transistor cannot be maintained, causing increased leakage
Solution Approach 1:
The power supply system is segmented into two independent power supply voltages: the first power supply voltage (SVDD) dedicated to the memory cell and its back gate, and the second power supply voltage (VDD) for the peripheral circuit. This segmentation allows the first power supply to remain active during standby to maintain the P-channel MOS transistor's threshold voltage through back gate biasing, while the second power supply can be shut off to reduce overall standby current.
Solution Approach 2:
The threshold voltage of the P-channel MOS transistor is dynamically controlled by changing the back gate voltage parameter. By applying the first power supply voltage to the back gate, the threshold voltage is maintained at an appropriate level even when the second power supply voltage is shut off during standby, preventing excessive leakage current while minimizing power consumption.
2Reliability
If the first power supply voltage is continuously supplied to maintain threshold voltage, then transistor performance is maintained, but standby current cannot be sufficiently reduced
Solution Approach 1:
The power supply is segmented into critical components (memory cell and back gate receiving first power supply voltage) and non-critical components (peripheral circuit receiving second power supply voltage). This allows selective power management where only the essential first power supply remains active during standby, significantly reducing overall standby current while maintaining necessary transistor performance.
Solution Approach 2:
Different power supply voltages are applied to different parts of the circuit based on their functional requirements. The memory cell and P-channel MOS transistor back gate receive continuous power through the first power supply to maintain data retention and threshold voltage, while the peripheral circuit receives power only during active operation through the second power supply, optimizing the balance between performance and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces standby current by maintaining a high threshold voltage for the P-channel MOS transistor even when the second power supply voltage is shut off, resulting in minimal power consumption during standby.
Implementation Method 1
a P-channel MOS transistor with a back gate receiving the first power supply voltage is used in the write/read circuit
Data Source
AI summary
In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small.