SRAM Cell Backside Interconnect Layout for Lower Contact Resistance
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, the tight spacing and high contact resistance in SRAM cells lead to high resistance and capacitance, resulting in low drive current and slow speed.
Innovation Solution
Incorporating both frontside and backside interconnect structures in SRAM cells, including backside contacts to sources of pull-down transistors and replacing frontside butted contacts with backside butted contacts, to improve electrical routing and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SRAM cell dimensions are scaled down to smaller technology nodes, then production efficiency is improved and costs are lowered, but contact resistance and capacitance increase leading to reduced drive current and slower speed
Solution Approach 1:
The patent introduces a backside interconnect structure that routes contacts from the backside of the substrate to the sources of pull-down transistors. This adds a vertical dimension (through-substrate routing) to the interconnect architecture, effectively reducing the lateral spacing constraints and contact resistance in scaled-down SRAM cells without sacrificing production efficiency
2Length of moving object
If contact structures are reduced in size to match smaller SRAM cell dimensions, then device scaling is achieved, but contact resistance increases and drive current decreases
Solution Approach 1:
By routing contacts through the backside of the substrate to reach transistor sources, the invention extends the contact path into the vertical dimension. This allows smaller lateral contact footprints while maintaining adequate contact area and low resistance through the through-substrate vias, thereby preserving drive current in scaled devices
Solution Approach 2:
The backside interconnect structure acts as an intermediary routing path between the contact structures and the transistor sources. This intermediate through-substrate connection layer enables optimized contact geometry that reduces resistance without increasing lateral dimensions
3Reliability
If frontside butted contacts are replaced with backside butted contacts, then contact resistance is reduced and saturation current increases, but manufacturing complexity increases
Solution Approach 1:
The invention moves the butted contact functionality from the frontside to the backside of the substrate, utilizing the vertical dimension to achieve lower resistance contacts. While this adds through-substrate via fabrication steps, it eliminates the need for complex frontside contact routing and enables better electrical performance
Data Source
AI summary
A semiconductor structure according to the present disclosure includes a first memory cell that includes a first pull-down transistor and a first pull-up transistor sharing a first gate structure extending along a first direction, a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the first direction, a first pass-gate transistor having a third gate structure spaced apart but aligned with the second gate structure along the first direction, and a second pass-gate transistor having a fourth gate structure spaced apart but aligned with the first gate structure along the first direction, a frontside interconnect structure disposed over the first memory device, a backside interconnect structure disposed below the first memory device. A source of the second pull-down transistor is electrically coupled to the backside interconnect structure by way of a first backside contact via.