SRAM Bias Circuit Stabilizes GND Potential via Segmentation
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Solution Overview
Problem
SRAM memory cells face retention characteristic deterioration due to leakage currents, which are exacerbated by variations in process conditions, voltage, and temperature, making it difficult to stabilize the power supply voltage within the cell array.
Innovation Solution
The implementation of a semiconductor memory structure with a bias circuit that includes specific configurations of PMOS and NMOS transistors to compensate for leakage currents, stabilizing the GND or VDD potential by adjusting the type and size of transistors to match the current amounts generated, and utilizing a ring oscillator and charge pump circuit to further stabilize the GND potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply voltage VDD is set lower to suppress leakage currents, then power consumption is reduced, but the retention characteristic deteriorates due to PVT variations
Solution Approach 1:
The invention divides the ground potential control into separate segments: a first ground potential for suppressing leakage currents and a second ground potential for stabilizing against PVT variations. This segmentation allows each ground potential to optimize for its specific function without compromising the other.
Solution Approach 2:
The invention dynamically adjusts the ground potential parameter based on operating conditions. By changing the ground potential level according to PVT variations, the system maintains optimal retention characteristics while keeping power consumption low.
2Object-generated harmful factors
If the power supply voltage VDD is set lower to suppress leakage currents, then leakage current is reduced, but the retention characteristic deteriorates due to PVT variations
Solution Approach 1:
The invention separates the functions of leakage suppression and retention stabilization by providing two distinct ground potentials. The first ground potential addresses leakage current suppression while the second ground potential maintains retention characteristics under PVT variations.
Solution Approach 2:
The invention implements feedback control by monitoring PVT variations and adjusting the second ground potential accordingly. This feedback mechanism ensures that retention characteristics are maintained despite changes in process conditions, voltage, or temperature.
3Device complexity
If traditional single ground potential method is used, then device complexity is low, but GND potential fluctuations are large under PVT variations
Solution Approach 1:
The invention segments the ground potential control into two independent potentials, allowing each to be optimized for its specific function. This segmentation improves GND potential stability without requiring complex dynamic adjustment mechanisms.
Solution Approach 2:
The invention adjusts the ground potential parameter to account for PVT variations. By changing the ground potential level adaptively, the system maintains stable GND potential despite environmental changes.
Data Source
AI summary
According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.