SRAM Bit Cell Row Segmentation for Power Optimization
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Solution Overview
Problem
Conventional SRAM modules waste power by pre-charging all bit cells in a row during memory access operations, even when only a subset is needed, leading to inefficient power consumption.
Innovation Solution
The SRAM module identifies the specific subset of bit cells required for the operation and enables only those cells via their corresponding wordlines, performing the memory access without pre-charging the remaining cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all bit cells in a row are pre-charged before memory access operation, then all bit cells can be accessed, but power consumption increases due to unnecessary pre-charging of non-targeted cells
Solution Approach 1:
The patent divides the bit cell row into multiple subsets, each accessible via a separate wordline. Instead of pre-charging all bit cells in the row, only the subset corresponding to the active wordline is pre-charged. This segmentation allows selective activation of bit cell groups, reducing unnecessary power consumption while maintaining full row accessibility.
Solution Approach 2:
The patent applies partial action by pre-charging only the necessary portion (subset) of bit cells required for the current memory access operation, rather than pre-charging the entire row. This partial pre-charging approach reduces power consumption while still enabling the required memory access function.
2Ease of operation
If the entire bit cell row is enabled for memory access, then all bit cells can be accessed, but power is wasted by enabling bit cells not required for the operation
Solution Approach 1:
The bit cell row is segmented into multiple subsets, each with its own wordline control. This segmentation enables selective enabling of only the necessary subset for the current operation, reducing power dissipation from enabling unnecessary cells while maintaining ease of access to any bit cell in the row.
Solution Approach 2:
The patent introduces dynamic control of wordlines to selectively enable different subsets of bit cells based on the current memory access requirements. This dynamic enabling approach allows the system to adapt to different access patterns and minimize power dissipation by activating only the necessary portion of the memory array.
Data Source
AI summary
A static read-only memory (SRAM) includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell row is coupled to two or more different wordlines, where each wordline associated with a given bit cell row provides memory access to a different subset of bit cells within that bit cell row.