SRAM Bit Cell Isolating Wall for Tighter Gate Pitch
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Solution Overview
Problem
Conventional SRAM bit cell designs occupy a large portion of the die surface area, limiting area efficiency and circuit density due to the precision limitations of gate cut techniques in reducing the spacing between channel tracks.
Innovation Solution
The use of dielectric walls to separate pass-gate and inverter gate electrodes, allowing for tighter pitch alignment and reduced lateral spacing between channel tracks, replacing the traditional gate cut method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate cut technique is used to separate gate electrodes, then manufacturing process is simpler, but spacing between channel tracks cannot be reduced sufficiently
Solution Approach 1:
The dielectric wall is formed in advance before the gate electrodes are created. This preliminary formation of the separating structure allows the gate electrodes to be positioned more closely together, as the dielectric wall provides a pre-established separation mechanism that does not rely on post-formation gate cutting operations.
Solution Approach 2:
A dielectric wall is introduced as an intermediary structure between the pass-gate electrode and the inverter gate electrode. This dielectric wall serves as a physical separator that enables tighter spacing between the conductive gate electrodes while maintaining electrical isolation, thus resolving the contradiction between reducing spacing and preventing short circuits.
2Area of stationary object
If dielectric wall is used to separate gate electrodes, then spacing between channel tracks can be reduced, but manufacturing process becomes more complex
Solution Approach 1:
The formation of the dielectric wall is merged with the existing trench isolation process used in semiconductor manufacturing. By utilizing the same trenching and fill operations already employed for device isolation, the additional separating structure is created using largely the same process steps, thereby minimizing the increase in manufacturing complexity.
Data Source
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Figure 3a
AI summary
A bit cell (10) for a Static Random-Access Memory, SRAM, is provided, comprising a first and second pair of complementary transistors as well as a first pass-gate transistor (PG1) and a second pass-gate transistor (PG2). A first inverter gate electrode (121) forms a common gate electrode for the first pair of complementary transistors and a second inverter gate electrode (122) forms a common gate electrode for the second pair of complementary transistors. Further, a first pass gate electrode (131) forms a gate of the first pass-gate transistor and a second pass gate electrode (132) forms a gate of the second pass-gate transistor. A first and a second dielectric wall (141, 142) are also provided, separating the first pass gate electrode from the first inverter gate electrode, and the second pass gate electrode from the second inverter gate electrode.