SRAM Bit Line Current Mirroring for Multi-Row In-Memory Compute
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Solution Overview
Problem
The simultaneous access of multiple rows in an SRAM array during in-memory compute operations leads to unwanted data flips due to excessive bit line voltage drops, compromising the accuracy of computational results, and existing solutions like word line underdrive or specialized bitcell designs have drawbacks such as reduced read current or increased circuit area.
Innovation Solution
An in-memory computation circuit with adaptive supply voltage and current mirroring circuits that inhibit voltage drops below the bit flip threshold during simultaneous word line actuation, using current mirroring to maintain stable bit line voltages and integrate read currents for accurate computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple rows are simultaneously accessed during in-memory compute operations, then computation throughput is improved, but bit line voltage drops excessively causing unwanted data flips
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging bit lines to a voltage level higher than the standard Vdd (e.g., Vdd + ΔV) before simultaneous row access. This pre-charging creates a voltage margin that compensates for the voltage drop occurring during concurrent read operations, preventing bit flip conditions while maintaining high computation throughput.
Solution Approach 2:
The patent changes the bit line voltage parameter from the standard Vdd to an elevated voltage level (Vdd + ΔV) during simultaneous access operations. This parameter change increases the voltage headroom available during concurrent reads, ensuring that even with multiple rows accessing the same bit lines simultaneously, the voltage remains above the threshold required to prevent unwanted data flips.
2Reliability
If word line underdrive is used to prevent data flips, then data accuracy is improved, but read current is reduced
Solution Approach 1:
Instead of applying word line underdrive (reducing word line voltage) to prevent data flips, the patent inverts the approach by elevating the bit line voltage above Vdd. This reverse strategy achieves the same data protection goal while actually increasing the read current available during operations, since the higher bit line voltage maintains stronger drive currents through the memory cells.
3Reliability
If specialized bitcell designs are used to prevent data flips, then data accuracy is improved, but circuit area is increased
Solution Approach 1:
The patent implements a universal solution that works with standard 6T SRAM bitcells without requiring specialized cell designs. By elevating the bit line voltage during simultaneous access, the same protection mechanism applies to all bitcells in the array regardless of their location or configuration, maintaining data accuracy while preserving the compact area benefits of conventional memory cell designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents unwanted data flips and maintains accurate read current levels, ensuring reliable in-memory compute operations without increasing circuit area, thus preserving computation performance and accuracy.
Implementation Method 1
a current mirroring circuit configured to mirror the bit line read current to generate a mirrored current
Implementation Method 2
an integration capacitor configured to integrate the mirrored current to generate an output voltage
Data Source
AI summary
An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.