Dual-Tracking SRAM Bit Line Timing for Lower Power Margins
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Solution Overview
Problem
The flying bit line scheme in SRAM architecture reduces memory area but introduces higher capacitance and resistance, leading to increased power consumption and timing issues due to shared timing circuits for fly and non-fly BL segments.
Innovation Solution
Implementing a dual tracking fly bit line SRAM architecture with separate timing circuits for fly and non-fly BL segments, ensuring precise timing and reducing over-margining, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a flying bit line scheme is used to reduce memory area, then the memory area is reduced, but the capacitance and resistance increase leading to higher power consumption
Solution Approach 1:
The bit line system is divided into two separate segments: fly BL segment and non-fly BL segment. Each segment has its own dedicated timing circuit (first tracking circuit for fly BL, second tracking circuit for non-fly BL), allowing independent optimization and control of each segment's operation to reduce overall power consumption while maintaining area efficiency.
2Device complexity
If a shared timing circuit is used for fly and non-fly BL segments, then the device complexity is reduced, but timing precision deteriorates causing over-margining
Solution Approach 1:
The timing control is segmented into separate tracking circuits for fly BL and non-fly BL segments. This segmentation enables each circuit to be optimized for its specific segment's timing requirements, achieving precise timing control without the over-margining that occurs with shared circuits, while the overall complexity remains manageable through modular design.
Data Source
AI summary
A memory circuit may comprise a memory array, a first tracking cell, a second tracking cell, a first tracking circuit, and a second tracking circuit. A first portion of the memory array may comprise a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction. A second portion of the memory array may comprise a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment both extending along the first lateral direction. The first tracking circuit can be configured to activate the first tracking cell, in response to at least one of the first nominal memory cells being selected. The second tracking circuit can be configured to activate the second tracking cell, in response to at least one of the second nominal memory cells being selected.