SRAM Global Bit-Line Pre-Charge Circuit for Power Reduction
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Solution Overview
Problem
SRAM arrays consume significant power due to the high pre-charging requirements of global bit-lines during read operations, which contributes substantially to the overall power consumption of processors where SRAM cells are used as caches.
Innovation Solution
A memory cell arrangement for SRAM cell groups where a shared global bit-line is pre-charged with a programmable voltage using a pre-charge circuit that includes a limiter circuit to compensate for leakage current without altering the voltage level, allowing for a lower pre-charge level that is independent of the power supply voltage and operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the global bit-line is pre-charged to full Vdd voltage, then the read operation reliability is improved, but the power consumption increases significantly
Solution Approach 1:
The patent changes the pre-charge voltage parameter from full Vdd to a reduced voltage level (e.g., Vdd/2 or programmable levels). The global bit-line is pre-charged to a voltage below full Vdd, and the read amplifier is designed to correctly interpret the differential signal at this reduced voltage level, thereby reducing power consumption while maintaining read operation reliability
Solution Approach 2:
The patent introduces programmable pre-charge voltage levels that can be dynamically adjusted based on operating conditions. The pre-charge circuit can select from multiple voltage levels (e.g., full Vdd, Vdd/2, or other programmable levels) to optimize the trade-off between reliability and power consumption under different workloads and process conditions
2Use of energy by moving object
If the pre-charge voltage is reduced, then the power consumption decreases, but the voltage level becomes dependent on power supply voltage and operating frequency
Solution Approach 1:
The patent introduces a pre-charge pump circuit as an intermediary between the power supply and the global bit-line. This pump circuit generates the reduced pre-charge voltage level independently of the main power supply voltage variations and frequency changes, providing a stable reference voltage that ensures consistent operation across different operating conditions
Solution Approach 2:
The pre-charge pump circuit is designed to automatically regulate and maintain the reduced pre-charge voltage level without requiring external control signals. The circuit self-adjusts to compensate for leakage currents and maintains the voltage level consistently, making the system adaptable to varying operating conditions without manual intervention
Data Source
AI summary
A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.