SRAM Bypass Redundancy for Synchronous-Write-Through Test Yield
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Solution Overview
Problem
Existing memory designs, particularly static random access memories (SRAMs), suffer from yield loss due to undetected defective synchronous-write-through (SWT) circuits during testing, as they are not adequately tested by memory tests and are misclassified as defective even if they do not affect normal SRAM function.
Innovation Solution
A memory design with built-in synchronous-write-through redundancy and a modified test flow that includes a logic test phase with fault analysis and soft repair, utilizing spare bypass circuits to replace defective SWT circuits, and a shared or dedicated programmable repair configuration register to manage redundancy, optimizing area usage and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a SWT circuit is used to provide a bypass path for bypassing an SRAM input to an SRAM output, then the test coverage for glue logic is improved, but the SWT circuit itself cannot be detected by memory tests and may be misclassified as defective
Solution Approach 1:
The patent introduces an intermediary test mechanism that specifically targets the SWT circuit functionality. A dedicated test mode is implemented that activates the SWT bypass path and verifies its operation separately from the main memory test. This intermediary testing approach allows the SWT circuit to be properly validated without interfering with the primary memory read/write test paths, thereby resolving the detection gap that caused yield loss.
Solution Approach 2:
The patent segments the testing process into distinct phases: a logic test phase that tests the SWT bypass functionality separately, and a memory test phase that tests the SRAM read/write functions. This segmentation allows each component (SWT circuit and SRAM array) to be tested independently with appropriate test patterns, preventing the misclassification of functional SWT circuits as defective due to inadequate testing.
2Measurement precision
If the SWT circuit is tested by logic test before memory test, then the glue logic can be covered, but the defective SWT circuit causes the die to be rejected even when the SRAM can pass memory test
Solution Approach 1:
The patent implements a dynamic test flow that adapts based on test results. After the initial logic test, if a failure is detected, the system dynamically switches to a more comprehensive SWT-specific test mode. Only if this secondary test confirms the defect is in the SWT circuit (not the SRAM array) does the system reject the die. This dynamic approach prevents premature rejection of functional SRAMs while maintaining high test coverage.
Solution Approach 2:
The patent changes the testing parameters and test patterns based on the test phase. During the logic test phase, specific test patterns are used to activate the bypass path. During the subsequent SWT verification phase, different test parameters are applied to specifically validate the SWT circuit functionality. This parameter adaptation allows for precise defect localization and prevents false failures that would reduce yield.
3Ease of operation
If the SWT circuit is located at a testing path rather than a real memory read/write function path, then the bypass function can be tested, but the memory test cannot detect the SWT circuit defects
Solution Approach 1:
The patent performs preliminary action by implementing a dedicated SWT verification test that is specifically designed to detect defects in the bypass circuit. This preliminary test is executed after the initial logic test but before final yield determination. The test pattern is pre-configured to activate the SWT path and verify its functionality, ensuring that SWT circuit defects are detected before the die is rejected, even though the SWT circuit is located on a testing path rather than the main memory read/write path.
Data Source
AI summary
A memory with built-in bypass redundancy includes a plurality of memory input/output (IO) arrays, a plurality of bypass circuits, and at least one spare bypass circuit. Each of the bypass circuits and the spare bypass circuit is used to provide a bypass path for bypassing a memory input to a memory output. The at least one spare bypass circuit is used to replace at least one of the plurality of bypass circuits that is defective.