SRAM Cell Area Reduction via Asymmetric Transistor Angles
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Solution Overview
Problem
Static-random-access memory (SRAM) cells occupy too much area due to rectilinear patterns, leading to lower memory cell density and suboptimal electronic performance, as transistors' channel lengths align with specific crystal planes that do not optimize electron and hole mobility.
Innovation Solution
Forming semiconductor fins and conductive members with channel lengths intersecting at angles other than integer multiples of 22.5°, allowing for more design flexibility and optimizing channel lengths along (100) and (110) crystal planes to enhance mobility and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If rectilinear patterns are used for semiconductor fins and conductive members, then manufacturing is simplified and alignment is easier, but SRAM cell area increases and memory density decreases
Solution Approach 1:
The patent applies asymmetry by orienting semiconductor fins and conductive members at non-orthogonal angles (e.g., 30°, 60°, 75°) relative to crystal planes, breaking the traditional rectilinear symmetry. This asymmetric orientation reduces the area occupied by each transistor while maintaining manufacturability through standardized fabrication processes.
Solution Approach 2:
The patent introduces angular orientation as an additional design dimension beyond the conventional orthogonal layout. By varying the angle of semiconductor fins and conductive members relative to crystal planes, the design optimizes both area utilization and electron mobility without compromising manufacturing simplicity.
2Reliability
If channel lengths are aligned with specific crystal planes (100) or (110), then electron and hole mobility is optimized, but design flexibility is reduced and SRAM cell area increases
Solution Approach 1:
The patent changes the angular parameter of channel orientation from fixed values (0° for <100>, 45° for <110>) to a continuous range of angles. This allows optimization of electron and hole mobility by selecting appropriate angles while providing design flexibility to accommodate different circuit requirements and area constraints.
Solution Approach 2:
The patent makes the channel orientation angle a dynamic design parameter that can be adjusted based on specific application requirements. Different transistors within the same SRAM cell can have different angular orientations optimized for their specific function (e.g., pull-up vs. pull-down transistors), enhancing overall cell performance.
3Reliability
If channel lengths are aligned with specific crystal planes, then transistor performance is optimized, but SRAM cell density decreases
Solution Approach 1:
By using asymmetric angular orientations for different transistor channels relative to crystal planes, the patent achieves compact transistor layouts that improve density. The asymmetric arrangement allows better packing of transistors within the SRAM cell while maintaining optimized carrier mobility through appropriate angle selection.
Data Source
AI summary
An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.