SRAM Cell Layout With Backside Power Wiring for Miniaturization
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Solution Overview
Problem
The miniaturization of SRAM cells is hindered by the decreasing margin between contacts and metal wirings, making it difficult to reduce the size of SRAM cells in CMOS processes.
Innovation Solution
A semiconductor device design that includes a substrate with specific active patterns and gate electrodes, shared source/drain patterns, and power supply wirings on different surfaces, allowing for a more efficient layout that reduces the need for overlapping connections and enhances design freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If six transistors are disposed in a single SRAM cell using CMOS process, then the SRAM cell can be formed with standard process, but the size of the SRAM cell cannot be reduced due to decreasing margin between contacts and metal wirings
Solution Approach 1:
The patent utilizes the thickness direction (vertical dimension) of the substrate by forming a bridge structure that extends in the third direction perpendicular to the first and second directions. This allows the bridge to connect source/drain regions that are spatially separated in the planar view, effectively using the third dimension to reduce planar area requirements while maintaining electrical connectivity.
Solution Approach 2:
The bridge structure serves multiple functions: it acts as a conductor for electrical connection, provides mechanical support for the gate electrode, and enables shared source/drain configurations between multiple transistors. This multi-functionality reduces the overall number of separate components needed, thereby reducing cell area.
2Area of moving object
If contacts and metal wirings are placed close together for miniaturization, then the SRAM cell size can be reduced, but the margin between contacts and metal wirings decreases leading to reliability issues
Solution Approach 1:
By forming the bridge structure that extends in the third direction (thickness direction), the patent creates vertical separation between the bridge and the substrate surface where contacts and metal wirings are located. This spatial separation in the vertical dimension allows for adequate clearance margins while maintaining compact planar dimensions.
Solution Approach 2:
The bridge structure acts as an intermediary element that provides electrical connection between source/drain regions without requiring direct planar contact between closely spaced contacts and metal wirings. This mediator approach allows for reduced planar spacing while maintaining reliable electrical connectivity through the elevated bridge structure.
3Area of moving object
If shared source/drain patterns and power supply wirings are implemented, then the SRAM cell area is reduced, but the wiring complexity increases
Solution Approach 1:
The bridge structure serves as a shared source/drain pattern for multiple transistors simultaneously, eliminating the need for separate source/drain regions for each transistor. This shared configuration reduces the total number of discrete wiring elements required, thereby reducing overall wiring complexity despite the area reduction.
Solution Approach 2:
The patent merges multiple source/drain regions into a single shared source/drain pattern that is common to multiple transistors. By combining these functions into unified structures, the total number of separate wiring connections is reduced, simplifying the overall wiring architecture despite the compact layout.
Data Source
AI summary
A semiconductor device may include a pass transistor on a first surface of the substrate, a pulldown transistor sharing an active region with the pass transistor, a pullup transistor sharing a gate with the pulldown transistor, a wordline connected to a gate of the pass transistor, a bitline connected to a drain of the pass transistor, a first power wiring on a second surface of the substrate and connected to a source of the pulldown transistor, and a second power wiring connected to a source of the pullup transistor. A source of the pass transistor and drains of the pulldown and pullup transistors may be connected through one node. The wordline, the bitline, and the second power wiring may be on the first surface of the substrate. A first portion the first power wiring may extend in a direction parallel to a gate of the pass transistor.