4X Contacted-Poly-Pitch SRAM Cell With Backside Routing
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) manufacturing is to reduce chip footprint while maintaining processing margins as technology nodes shrink, particularly in static random-access memory (SRAM) cells, where complexity increases with scaling down.
Innovation Solution
The implementation of multi-gate transistors, such as FinFET or vertically stacked multiple channels gate-all-around transistors, along with innovative metal layer arrangements that relocate conductors to the back-side of the SRAM cells, reducing routing loading and cell size, and utilizing isolation transistors with dummy dielectric gate structures to improve device stability and reduce resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistors are used in SRAM cells, then manufacturing process is simpler, but chip footprint is larger and processing margins are reduced
Solution Approach 1:
The patent transitions from planar two-dimensional transistor layouts to three-dimensional FinFET structures and vertically stacked multi-channel gate-all-around transistors. This dimensional change enables higher device density within the same chip footprint while maintaining manufacturability through established FinFET fabrication processes
Solution Approach 2:
The patent implements vertically stacked multi-channel transistors where multiple active channels are stacked one above another and surrounded by a common gate structure. This nesting arrangement packs multiple transistor channels into a single vertical column, dramatically reducing the horizontal chip area required per transistor while keeping the manufacturing process relatively simple
2Area of moving object
If chip scaling is pursued to increase device density, then chip footprint is reduced, but processing complexity increases
Solution Approach 1:
By moving to vertical FinFET and stacked transistor architectures, the patent achieves higher effective device density without proportionally increasing processing steps. The vertical structure allows standard planar lithography to pattern the base layer while subsequent self-aligned processes form the three-dimensional structures, avoiding the need for entirely new complex fabrication methodologies
Solution Approach 2:
The patent divides the transistor channel into multiple vertically stacked segments, each surrounded by its own gate in gate-all-around structures. This segmentation allows independent optimization of each channel segment and enables higher density packing while using modular, repeatable fabrication steps for each segment layer
3Area of moving object
If multi-gate transistors are implemented, then device density increases, but routing complexity and capacitance increase
Solution Approach 1:
The patent relocates metal interconnect conductors from the front-side to the back-side of the SRAM cell structure. This three-dimensional routing arrangement separates signal paths and reduces capacitive coupling between adjacent interconnects, lowering routing complexity and capacitance despite the high density of vertical transistor structures
Solution Approach 2:
The patent introduces dummy dielectric gate structures adjacent to isolation transistors that serve as electrical isolators. These dummy gates act as intermediaries that prevent unwanted electrical coupling and reduce parasitic capacitance between adjacent transistor regions, simplifying the overall routing environment
4Area of moving object
If component size is reduced to increase density, then chip footprint is reduced, but resistance and capacitance increase
Solution Approach 1:
The patent uses vertical FinFET channels and stacked transistor structures that provide longer effective channel lengths within smaller horizontal footprints. The three-dimensional channel geometry increases the channel area for current conduction while maintaining electrical isolation, thereby reducing resistance and capacitance effects despite compact dimensions
Solution Approach 2:
The patent employs dummy dielectric gate structures filled with insulating materials adjacent to isolation transistors. These composite dielectric structures reduce parasitic capacitance and improve electrical isolation between adjacent devices, enhancing device stability in the reduced-size SRAM cell configuration
Data Source
AI summary
An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.