SRAM Cell Compute-in-Memory for Voice Recognition
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Solution Overview
Problem
Existing voice recognition systems face challenges in achieving efficient processing speed and low power consumption due to the von Neumann bottleneck and the need for high-bandwidth data transfer.
Innovation Solution
A recognition system utilizing SRAM cells with charge redistribution to generate an accumulated signal, combined with a quantizer that includes a shared capacitor array, to reduce power consumption and enhance bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If computation and memory are separated (von Neumann architecture), then system reliability is improved, but processing speed and energy efficiency deteriorate due to the von Neumann bottleneck
Solution Approach 1:
The patent merges computation and memory into a unified structure by implementing compute-in-memory circuits within the SRAM cell array. Weight values are stored directly in the SRAM cells, and multiplication operations are performed through analog current summation during read operations, eliminating the need to transfer data between separate memory and computation units.
2Adaptability or versatility
If data is transferred between memory and computation units, then system modularity is improved, but energy consumption increases due to continuous data movement
Solution Approach 1:
The patent combines storage and computation functions within the same physical location (SRAM cell array). Weight values are stored in SRAM cells and multiplied with input signals through analog current summation during read operations, eliminating energy-consuming data transfers between separate memory and computation units.
Solution Approach 2:
The patent replaces digital data transfer mechanisms with analog signal processing. Instead of reading weight values digitally and performing multiplication in a separate processor, the system uses analog current summation where currents representing weight values are summed directly at the bit line, performing computation through physical signal aggregation rather than digital processing.
3Productivity
If data transfer bandwidth is increased, then processing throughput is improved, but power consumption and system complexity increase
Solution Approach 1:
The patent replaces high-bandwidth digital data transfer with low-bandwidth analog signal processing. Weight values are multiplied with input signals through analog current summation during read operations, achieving high throughput without requiring high data transfer bandwidth between memory and computation units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed system achieves reduced power consumption and enhanced bandwidth by integrating computation and memory, allowing for efficient processing of voice recognition tasks.
Implementation Method 1
SRAM cells adopting charge redistribution to generate an accumulated signal
Implementation Method 2
the quantizer including at least one capacitor array
Data Source
AI summary
A static random-access memory (SRAM) cell includes a first inverter and a second inverter being cross-coupled; a first access transistor that accesses an output of the first inverter under control of a word line; a second access transistor that accesses an output of the second inverter under control of the word line; a first passage transistor that passes a common-mode voltage, controlled by the output of the first inverter; a second passage transistor that passes an input signal, controlled by the output of the second inverter; and a capacitor switchably coupled to receive the common-mode voltage and the input signal through the first passage transistor and the second passage transistor respectively.