SRAM Cell Layout With Dummy Structures for Low Leakage
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Solution Overview
Problem
The challenge of achieving high read and write speeds in Static Random Access Memory (SRAM) cells is exacerbated by the down-scaling of already small cells, leading to issues such as non-necessary leakage currents and poor device matching, which affect performance and stability.
Innovation Solution
The implementation of a semiconductor device with specific layouts and configurations, including gate-all-around structures and optimized conductive segments, reduces leakage currents and improves device symmetry, thereby enhancing cell scaling and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If SRAM cells are down-scaled to increase integration density, then device size is reduced, but leakage currents increase and device matching deteriorates
Solution Approach 1:
The patent applies asymmetry by intentionally introducing dummy structures (dummy gates, dummy contacts, dummy vias) around the scaled-down SRAM cells. These dummy structures are strategically placed to compensate for the disproportionate impact of edge effects and quantum confinement that occur during down-scaling. The asymmetric distribution of these compensating structures helps balance the electrical characteristics and reduce leakage currents that would otherwise increase with cell size reduction.
Solution Approach 2:
The patent employs parameter changes by modifying the physical dimensions and material properties of the dummy structures to match and compensate for the scaled-down SRAM cell parameters. The dummy structures are designed with specific widths, lengths, and spacing that are calibrated to offset the increased leakage and matching issues caused by cell down-scaling, effectively changing the local electrical parameters to maintain performance.
2Area of moving object
If SRAM cells are down-scaled to increase integration density, then device size is reduced, but device matching deteriorates
Solution Approach 1:
The patent applies asymmetry by intentionally introducing dummy structures (dummy gates, dummy contacts, dummy vias) around the scaled-down SRAM cells. These dummy structures are strategically placed to compensate for the disproportionate impact of edge effects and quantum confinement that occur during down-scaling. The asymmetric distribution of these compensating structures helps balance the electrical characteristics and reduce leakage currents that would otherwise increase with cell size reduction.
Solution Approach 2:
The patent employs parameter changes by modifying the physical dimensions and material properties of the dummy structures to match and compensate for the scaled-down SRAM cell parameters. The dummy structures are designed with specific widths, lengths, and spacing that are calibrated to offset the increased leakage and matching issues caused by cell down-scaling, effectively changing the local electrical parameters to maintain performance.
3Ease of manufacture
If conventional SRAM cell structures are used, then manufacturing is simpler, but read/write speeds are insufficient for high-speed applications
Solution Approach 1:
The patent applies the nesting principle by integrating dummy structures within and around the SRAM cell layout in a hierarchical manner. The dummy gates are nested between actual cell gates, dummy contacts are nested in the contact layer, and dummy vias are nested in the via layer. This nested arrangement allows the dummy structures to be incorporated into the existing multi-layer fabrication process without requiring additional manufacturing steps, thereby maintaining manufacturing simplicity while improving cell performance through reduced RC effects.
Data Source
AI summary
A semiconductor device includes first and second active areas, first and second gate structures, and first to third conductive segments. The first and second active areas extend along the first direction. The first and second gate structures cross over the first and second active areas. The first conductive segment crosses over the first and second gate structures, stores a first data signal, and is coupled to the first gate structure, the first and second active areas. The second conductive segment crosses over the first and second gate structures, stores a first complementary data signal, and is coupled to the second gate structure, the first and second active areas. The third conductive segment crosses over the first and second gate structures, and is coupled to the second active area. The first to third conductive segments are arranged in order along a second direction different from the first direction.