Dynamic Supply Voltage for SRAM Write Margin and Leakage

Solution Overview

Problem

SRAM cell performance is limited at low supply voltages due to the compromise between write port sizing and current leakage, where the p-channel transistor strength is insufficient to overcome the slowest n-channel passgate transistor, affecting write time and overall performance.

Innovation Solution

A circuit and method that dynamically apply different supply voltages to the true and complement data storage nodes based on the logic state being written, with higher voltages applied for writing logic high values and lower voltages for logic low values, and apply different body bias voltages to enhance the strength of the p-channel pullup transistors during write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the passgate n-channel transistor is made larger to overcome the slowest write operation, then write margin is improved, but current leakage increases and occupied area increases

Engineering Contradiction:

Improvewrite marginVSAvoidcurrent leakage

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies dynamic voltage adjustment to the p-channel pullup transistor during write operations. The supply voltage to the pullup transistor is dynamically changed based on the write operation status, allowing the transistor strength to be adjusted in real-time. This enables the use of a smaller passgate transistor while achieving sufficient write margin, thereby reducing leakage and occupied area.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of the p-channel pullup transistor during write operations. By adjusting the supply voltage to the pullup transistor, the transistor's effective strength is modified to overcome the slowest write operation. This parameter change allows the system to achieve improved write margin without increasing the passgate transistor size, thus avoiding increased leakage and area.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the passgate n-channel transistor is made larger to overcome the slowest write operation, then write margin is improved, but occupied area increases

Engineering Contradiction:

Improvewrite marginVSAvoidoccupied area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies dynamic voltage adjustment to the p-channel pullup transistor during write operations. The supply voltage to the pullup transistor is dynamically changed based on the write operation status, allowing the transistor strength to be adjusted in real-time. This enables the use of a smaller passgate transistor while achieving sufficient write margin, thereby reducing occupied area.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of the p-channel pullup transistor during write operations. By adjusting the supply voltage to the pullup transistor, the transistor's effective strength is modified to overcome the slowest write operation. This parameter change allows the system to achieve improved write margin without increasing the passgate transistor size, thus avoiding increased occupied area.

Inventive Principle:

Principle #35Parameter changes

3Loss of energy

If the p-channel transistor is made weaker to reduce occupied area and leakage, then area and leakage are reduced, but write time increases and performance decreases

Engineering Contradiction:

Improvecurrent leakageVSAvoidwrite time

Core Design Contradiction:

Loss of energyVSProductivity

Solution Approach 1:

The patent applies dynamic voltage adjustment to the p-channel pullup transistor during write operations. The supply voltage to the pullup transistor is dynamically changed based on the write operation status, allowing the transistor strength to be adjusted in real-time. This enables the use of a weaker (smaller) pullup transistor that reduces leakage, while during write operations the voltage is adjusted to ensure sufficient write speed, thus improving write time and performance.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8724374B1Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell

Publication Date: 2014.05.13 STMICROELECTRONICS INT NV

AI summary

A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.