SRAM ECC Checkbit Redundancy for Malfunction Detection
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Solution Overview
Problem
Existing memory circuits lack sufficient detection mechanisms for malfunctions, such as incorrect data addressing and chip select issues, which can lead to unpredictable behavior and data loss, as error correction codes (ECC) fail to detect these faults.
Innovation Solution
A memory system comprising a first memory, a second memory, and a memory controller circuit that writes ECC checkbits to both memories and a comparator circuit to perform a bit-by-bit comparison of ECC checkbits from both memories, generating a signal indicating a malfunction if a mismatch is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC is used to correct bit errors in application data, then data accuracy is improved, but the system cannot detect malfunctions such as incorrect addressing or chip select issues
Solution Approach 1:
The patent introduces ECC checkbits as an intermediary element that serves dual purposes: correcting bit errors in application data and detecting memory malfunctions. The checkbits act as a mediator between the application data and the memory system, providing additional information that enables both error correction and malfunction detection without requiring separate mechanisms.
Solution Approach 2:
The ECC checkbits are designed to perform multiple functions simultaneously: they correct single-bit errors in application data and detect malfunctions such as incorrect addressing and chip select issues. This multi-functionality eliminates the need for separate error correction and malfunction detection systems, resolving the contradiction between improving data accuracy and enabling malfunction detection.
2Difficulty of detecting and measuring
If a second memory is added to store redundant ECC checkbits, then malfunction detection capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into a first memory for storing application data and a second memory for storing redundant ECC checkbits. This segmentation allows each memory to have a specialized function, with the second memory dedicated solely to storing checkbits for malfunction detection, thereby improving detection capability while organizing complexity into manageable segments.
Solution Approach 2:
The patent creates a copy of the ECC checkbits in a second memory, separate from the first memory that stores application data. This copying approach enables independent verification of memory operations by comparing checkbits from both memories, improving malfunction detection while using a simple duplication strategy rather than complex verification logic.
Data Source
AI summary
Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.