SRAM Cells with Embedded ROM via N-Well Biasing
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Solution Overview
Problem
Current semiconductor devices require dedicated area for separate SRAM and ROM circuitry, leading to inefficient use of space, especially as devices become smaller, and involve additional routing metal for functionality.
Innovation Solution
Embedding ROM functionality within SRAM cells by biasing N-wells to switch between SRAM and ROM modes using shared peripheral circuitry, eliminating the need for additional routing metal and reducing area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate SRAM and ROM circuitry are implemented on the same IC die, then both memory types can be integrated, but the device area increases due to dedicated circuitry for each memory type
Solution Approach 1:
The patent implements a universal memory cell structure that can function as either SRAM or ROM based on the state of N-well biasing. The same physical memory cells are used for both memory types, eliminating the need for separate dedicated circuitry. When N-wells are unbiased, the cells operate as SRAM; when N-wells are biased, they operate as ROM, thus achieving multi-functionality with a single circuit implementation.
Solution Approach 2:
The patent merges SRAM and ROM functionalities into a single integrated memory array by combining the circuit structures. The memory cells share common components including transistors, bit lines, word lines, and peripheral circuitry. The N-well regions are integrated into the existing SRAM cell structure, allowing both memory types to coexist in the same physical space without requiring separate dedicated areas.
2Reliability
If dedicated area is allocated for each memory type, then independent functionality is achieved, but space efficiency decreases
Solution Approach 1:
The memory cells are designed with universal functionality to operate in either SRAM or ROM mode depending on N-well biasing conditions. This eliminates the need for separate dedicated areas while maintaining independent functionality through mode switching controlled by the biasing state of the N-well regions.
3Adaptability or versatility
If additional routing metal is added for ROM functionality, then ROM operations are enabled, but device complexity and area increase
Solution Approach 1:
The same routing infrastructure (bit lines, word lines, and interconnects) is used for both SRAM and ROM operations. The N-well biasing mechanism enables ROM functionality without requiring additional routing metal, as the existing SRAM routing structure suffices for both memory types when operated in their respective modes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient use of space by allowing memory cells to function as either SRAM or ROM depending on biasing, reducing area needs and eliminating the need for additional routing, thereby optimizing memory module design.
Implementation Method 1
When the array of SRAM cells is powered up in ROM mode, the N-wells of the cells are biased and data stored in the embedded ROM can be read using SRAM peripheral circuitry.
Data Source
AI summary
An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.