SRAM Eviction Allocation Using Overlapped Read-Write Cycles
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Solution Overview
Problem
Existing memory eviction and allocation processes in SRAM are inefficient, requiring multiple cycles for read and write operations, leading to increased latency and reduced throughput.
Innovation Solution
Implementing a 'blast mode' in memory circuitry that allows simultaneous read and write operations on multiple columns of a wordline, utilizing a control circuit with a state machine to coordinate read and write operations, enabling concurrent loading of data into input registers during the read phase, thereby reducing the total cycle count for eviction and allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential read and write operations are performed in SRAM, then data integrity is maintained, but latency increases and throughput decreases
Solution Approach 1:
The patent loads data into input registers during the read operation phase, before the write operation is actually executed. This preliminary action allows the write data to be ready and staged when the write phase begins, eliminating the need to wait for read completion before preparing write data, thus reducing total operation time and increasing throughput
Solution Approach 2:
The patent implements a state machine that manages overlapping read and write operations, ensuring that while read operations are in progress, write data is simultaneously being loaded into registers. This continuous utilization of circuit resources without idle waiting periods maintains high productivity while managing the sequential nature of SRAM operations
2Productivity
If individual read and write operations are performed separately, then operation reliability is maintained, but the number of cycles increases
Solution Approach 1:
The patent introduces a control circuit with a state machine that acts as an intermediary between the read and write operations. This state machine coordinates the timing and sequencing of operations, managing the complexity of overlapping operations while allowing the main memory array to perform simpler, more reliable individual read and write operations
Solution Approach 2:
The control circuit is designed to handle multiple operation modes including traditional sequential operations and optimized overlapping operations. The state machine can manage different operation sequences and data paths, providing a universal control mechanism that handles both simple and complex operation scenarios without requiring separate dedicated circuits for each mode
Data Source
AI summary
A method of performing an eviction allocation in memory can include receiving, at memory circuitry, control inputs indicating an eviction allocation operation including a read operation from a plurality of addresses and a write operation to a same plurality of addresses; in response to receiving the control inputs indicating the eviction allocation operation, performing the read operation of the plurality of addresses; and while performing the read operation of the plurality of addresses, loading data to be written to the same plurality of addresses into input registers of write circuitry of the memory circuitry. After a final word is read from the plurality of addresses, the data loaded into the input registers during the read operation can be written to the plurality of addresses.