Standard Cell and SRAM Fin Layout for Speed-Leakage Balance
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Solution Overview
Problem
The increasing complexity and miniaturization of SRAM cells in integrated circuits pose challenges in achieving high read and write speeds, as the smaller dimensions make it difficult to maintain performance.
Innovation Solution
The use of P-type FinFETs with SiGe channel material in standard cells and non-SiGe channel material in SRAM cells, where the semiconductor fins are configured differently to optimize performance for each type of cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If SRAM cells are downscaled to reduce geometric size, then area is reduced, but read speed and write speed become difficult to achieve
Solution Approach 1:
The patent applies different fin structure configurations to different transistor types within the SRAM cell. Specifically, first fins are provided for first transistors (pull-up transistors) with different characteristics than second fins for second transistors (pass transistors). This local differentiation allows optimization of speed performance while maintaining downscaled dimensions, as each fin structure can be tuned for its specific transistor function.
Solution Approach 2:
The patent changes physical parameters of the fin structures, including fin width, fin length, and fin spacing, to optimize SRAM cell performance at scaled dimensions. By adjusting these parameters, the patent achieves improved read and write speeds while maintaining the reduced geometric size required for high-density integration.
2Quantity of substance
If SRAM cells are downscaled to increase functional density, then area is reduced, but maintaining performance becomes difficult
Solution Approach 1:
The patent implements local quality differentiation by providing distinct fin structures for different transistor locations within the SRAM cell. First fins for pull-up transistors have different dimensions and characteristics compared to second fins for pass transistors. This localized optimization ensures reliable performance across all transistors even as the overall cell size is reduced to increase functional density.
Solution Approach 2:
The patent segments the fin structure into multiple distinct types (first fins and second fins) with different characteristics. This segmentation allows each fin type to be independently optimized for its specific transistor function, ensuring that performance requirements are met across the entire SRAM cell while maintaining high functional density through compact overall dimensions.
3Speed
If standard cells use SiGe channel material to enhance speed, then speed is improved, but leakage increases
Solution Approach 1:
The patent applies local quality by providing different fin structures for different transistor types. First fins for pull-up transistors are optimized for high-speed operation using SiGe channel material to enhance switching speed, while second fins for pass transistors use different characteristics to minimize leakage. This spatial differentiation of fin properties allows simultaneous optimization of speed and leakage control in different parts of the circuit.
Data Source
AI summary
An integrated circuits (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.