SRAM Bit-Cell Read Margin via High-K Spacer Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The area scaling of SRAM bit-cells is limited by read stability, and conventional methods to address this, such as under-driving the word-line voltage, degrade SRAM performance by reducing bit-cell read current and increasing resistance, limiting design space for performance versus density trade-offs.
Innovation Solution
Increasing the capacitance between storage nodes of SRAM bit-cells using High-K materials for spacers and integrating 3D Metal-Insulator-Metal capacitors, while reducing bit-line capacitance with Low-K materials, to enhance read noise margin without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If WL voltage is lowered to improve read margin, then read stability is improved, but read current is reduced and performance is degraded
Solution Approach 1:
The patent applies different dielectric materials with different K values to different regions of the bit-cell. High-K material is used for storage node capacitors to maximize capacitance and improve read stability, while Low-K material is used for bit-line capacitors to minimize parasitic capacitance and maintain fast read performance. This spatial differentiation of material properties resolves the contradiction between read stability and read performance.
Solution Approach 2:
The patent employs a composite dielectric structure combining High-K and Low-K materials within the same bit-cell architecture. The storage node capacitors utilize High-K dielectric material to achieve high capacitance density for improved read margin, while bit-line capacitors use Low-K dielectric material to reduce parasitic effects. This composite approach allows simultaneous optimization of both read stability and read performance.
2Quantity of substance
If area scaling is pursued to increase density, then SRAM density is improved, but read stability is degraded
Solution Approach 1:
The patent changes the dielectric parameter (K value) of the capacitor materials to achieve higher capacitance density without increasing physical area. By using High-K material for storage node capacitors, the patent achieves superior read stability in scaled bit-cells where area is constrained. This parameter change allows density improvement while maintaining read stability through enhanced capacitance per unit area.
3Reliability
If High-K material is used for storage node capacitors, then read noise margin is improved, but parasitic capacitance increases
Solution Approach 1:
The patent strategically places High-K material only in regions where high capacitance is beneficial (storage node capacitors), while using Low-K material in regions where parasitic capacitance is harmful (bit-line capacitors). This localized material selection improves read noise margin through enhanced storage node capacitance while minimizing parasitic capacitance effects on bit-line performance.
Solution Approach 2:
The patent creates a composite capacitor structure where High-K dielectric is used for storage node capacitors to maximize capacitance and improve read noise margin, while Low-K dielectric is used for bit-line capacitors to minimize parasitic capacitance. This composite material approach resolves the contradiction between improving read noise margin and reducing parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves read noise margin and enables high-speed operation for minimal-area SRAM bit-cells without degrading performance, allowing for better design flexibility between density and performance.
Implementation Method 1
Increasing the capacitance between storage nodes of SRAM bit-cells using High-K materials for spacers
Implementation Method 2
using High-K materials for spacers and integrating 3D Metal-Insulator-Metal capacitors
Implementation Method 3
reducing bit-line capacitance with Low-K materials
Data Source
AI summary
Described is a 6T SRAM cell which comprises: a first n-type transistor with a gate terminal coupled to word-line, source/drain terminal coupled to a first bit-line and drain/source terminal coupled to a first node; and a second n-type transistor with a source terminal coupled to a first supply node, a drain terminal coupled to the first node, and a gate terminal for coupling to multiple terminals, wherein the gate terminal includes a capacitor to increase coupling capacitance of the second n-type transistor. Described is a method which comprises: forming a metal gate in a first direction; forming a first spacer in the first direction on one side of the metal gate, the first spacer having a first dimension; and forming a second spacer in the first direction on another side of the metal gate, the second spacer having a second dimension which is substantially different from the first dimension.