SRAM Layout Pattern with Variable Gate Lengths for Current Consistency
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Solution Overview
Problem
Current SRAM architectures face challenges in maintaining consistent current levels across different regions due to layout differences, affecting exposure quality and manufacturing yield.
Innovation Solution
The proposed solution involves a layout pattern for SRAM that includes a latch circuit with transistors of varying gate lengths, where an Optical Proximity Correction (OPC) process and ion implantation are used to adjust gate lengths and threshold voltages, respectively, to minimize current differences between inner and outer regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SRAM layout is used, then manufacturing process is simple, but current differences in different regions occur due to layout variations
Solution Approach 1:
The patent applies local quality by differentiating the gate lengths of access transistors based on their specific positions within the SRAM cell. Inner access transistors (PG2A, PG2B) have a first gate length while outer access transistors (PG1A, PG1B) have a second gate length. This localized variation compensates for current differences caused by layout variations, achieving better current consistency across different regions without requiring complete redesign of the entire layout structure.
Solution Approach 2:
The patent changes the gate length parameter of access transistors to adjust and balance current flow. Specifically, inner access transistors are designed with a different gate length than outer access transistors, allowing precise control over current characteristics in different regions of the SRAM cell. This parameter adjustment directly addresses the current inconsistency problem while maintaining overall layout simplicity.
2Quantity of substance
If pitch of exposure process is decreased, then SRAM density is increased, but exposure quality deteriorates
Solution Approach 1:
The patent addresses exposure quality issues at reduced pitch by applying different gate lengths to transistors in different locations within the SRAM cell. This local differentiation compensates for exposure process variations that occur at smaller pitch sizes, allowing higher SRAM density to be achieved while maintaining acceptable manufacturing precision and current consistency.
3Manufacturing precision
If gate lengths are made different in inner and outer regions, then current differences are reduced, but transistor design complexity increases
Solution Approach 1:
The patent implements local quality by assigning different gate lengths only to specific access transistors (inner vs. outer) while keeping other transistors in the latch circuit with standard dimensions. This targeted approach reduces current differences between regions without requiring all transistors to be redesigned, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The patent changes the gate length parameter selectively for access transistors to achieve current balancing. By modifying only the gate length parameter of specific transistors rather than redesigning entire transistor structures or changing multiple parameters simultaneously, the solution achieves current consistency with minimal increase in design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces current disparities and enhances SRAM quality by optimizing gate lengths and threshold voltages, thereby improving the consistency and efficiency of current flow within the SRAM structure.
Implementation Method 1
an ion implantation process is performed on the first inner access transistor or to the second inner access transistor
Data Source
AI summary
The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.