SRAM Negative Bit-Line Circuit with Dynamic Capacitance Switching
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Solution Overview
Problem
The traditional negative bit line (NBL) scheme in SRAM design leads to increased capacitance on the voltage line, reducing kick efficiency and increasing power consumption due to direct coupling of capacitors to the voltage line.
Innovation Solution
Implementing a switch circuit that dynamically connects and disconnects capacitors to the negative voltage line based on kick signals and an enable signal, regulating the capacitance of the electric path to improve NBL kick efficiency and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are directly coupled to the voltage line to achieve NBL scheme, then write capability is improved, but capacitance on the voltage line increases
Solution Approach 1:
The patent divides the capacitor coupling into two separate paths: one path couples the first capacitor to the first voltage line, and another path couples the second capacitor to the second voltage line. This segmentation prevents the capacitors from being directly coupled to a single voltage line, thereby reducing the total capacitance on each voltage line while maintaining the NBL scheme's write capability through differential operation.
Solution Approach 2:
The patent introduces a capacitor coupling structure as an intermediary element between the voltage lines and the bit cells. This intermediary capacitor couples the voltage lines to the bit cells in a controlled manner, enabling the NBL scheme to function while limiting the direct capacitive loading on the voltage lines compared to traditional direct coupling approaches.
2Reliability
If capacitors are directly coupled to the voltage line, then NBL scheme is achieved, but kick efficiency decreases
Solution Approach 1:
The patent segments the capacitive coupling arrangement so that capacitors are distributed across different voltage lines rather than concentrated on a single voltage line. This segmentation reduces the total capacitance burden on each voltage line, thereby improving kick efficiency while maintaining the NBL scheme's functionality through differential voltage operation.
Solution Approach 2:
The patent changes the capacitance parameter distribution by using separate capacitors on separate voltage lines instead of large capacitors on a single voltage line. This parameter change optimizes the RC time constant of the voltage lines, improving the speed and efficiency of voltage transitions (kick efficiency) while preserving the NBL write capability.
3Reliability
If capacitors are directly coupled to the voltage line, then NBL scheme is implemented, but power consumption increases
Solution Approach 1:
The patent segments the capacitive loading across multiple voltage lines, reducing the capacitance on each individual line. This reduces the energy required to charge and discharge each voltage line during write operations, thereby lowering overall power consumption while maintaining the NBL scheme's write capability through differential operation.
Solution Approach 2:
The patent converts the potentially harmful effect of high capacitance (which increases power consumption) into a beneficial differential structure. By using matched capacitors on matched voltage lines with opposite polarity swings, the common-mode noise and power consumption are reduced, while the differential signal maintains effective write capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dynamic regulation of capacitance enhances NBL kick efficiency and reduces power consumption by optimizing the voltage change on the negative voltage line and bit lines, allowing for more efficient write operations.
Implementation Method 1
a first capacitive unit (122) and a second capacitive unit (124)... pulling down a voltage of a negative voltage line (NVSS) to a negative voltage level
Data Source
AI summary
A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.