Shared SRAM Pick-Up Regions for Stable Well Potentials
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Solution Overview
Problem
As integrated circuits (ICs) become smaller and more densely packed, leakage current issues between adjacent n-type and p-type wells in pick-up regions of static random-access memory (SRAM) devices increase, leading to higher resistance and deteriorated device performance.
Innovation Solution
Implementing shared pick-up regions using gate-all-around (GAA) and fin field-effect transistors (finFET) devices, which are placed adjacent to or in contact with n-type and p-type wells, reducing leakage current and enhancing carrier mobility, while allowing both peripheral circuits and SRAM cells to access these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are made smaller and more densely placed to increase device density, then device density increases, but leakage current between adjacent n-type and p-type wells increases
Solution Approach 1:
An n-type pick-up region is introduced as an intermediary structure between adjacent n-type and p-type wells. This pick-up region acts as a mediator that prevents direct leakage current paths between the wells while maintaining the dense transistor placement. The pick-up region is coupled to an n-type well and positioned to intercept and redirect leakage currents, thereby protecting the adjacent wells from harmful leakage effects.
Solution Approach 2:
The patent replaces traditional well-isolation mechanisms with a field-effect-based solution using GAA and finFET devices. Instead of relying solely on physical separation or deep trench isolation, the invention uses the electric field control capability of advanced transistor structures to manage carrier distribution and suppress leakage currents through their gate control mechanisms.
2Stability of the object's composition
If traditional pick-up regions are used in densely packed ICs, then well potential stabilization is achieved, but device footprint increases
Solution Approach 1:
The pick-up region is merged with the peripheral circuit structures, allowing shared usage of the same physical region for both pick-up functionality and circuit operations. This merging eliminates the need for separate dedicated pick-up regions, thereby stabilizing well potentials without increasing the overall device footprint.
Solution Approach 2:
The pick-up region is designed to serve multiple functions: it stabilizes well potentials, provides a path for charge distribution, and can be integrated with peripheral circuit elements. This multi-functionality allows the same structure to perform several roles, reducing the total area required compared to dedicated single-function regions.
3Reliability
If GAA and finFET devices are used in pick-up regions, then carrier mobility is enhanced and leakage is reduced, but device complexity increases
Solution Approach 1:
Advanced GAA and finFET transistor structures are applied locally only in the pick-up regions where leakage control and carrier mobility enhancement are most critical, rather than throughout the entire device. This localized application provides the performance benefits where needed while limiting the increase in overall device complexity to specific areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes well potentials, facilitates uniform charge distribution, reduces device footprint, and increases device density, thereby improving SRAM performance and efficiency.
Implementation Method 1
facilitates uniform charge distribution
Implementation Method 2
reduces leakage current
Implementation Method 3
enhancing carrier mobility
Data Source
AI summary
The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.